During an output short-circuit event, the current through the device increases very rapidly. When an output short-circuit is detected, the internal fast-trip comparator triggers a fast protection sequence to prevent the current from building up further and causing any damage or excessive input supply droop. This action enables the user to adjust the fast-trip threshold as per system rating, rather than using a high fixed threshold which may not be suitable for all systems. The fast-trip comparator employs a scalable threshold (I_SFT) which is a function of the circuit-breaker threshold (I_OCP) and a digitally programmable scaling factor. The default fast-trip threshold is equal to 2 × I_OCP during steady-state and 1.5 × I_LIM during inrush. The scaling factor for steady-state fast-trip threshold can be programmed to a different value using the DEVICE_CONFIG[12:11] register bits. Available programming options are 1.5 ×, 2 ×, 1.75 × and 2.25 ×. After the current exceeds the fast-trip threshold, the TPS25990 turns off the FET within t_SFT.

The device also employs a higher fixed fast-trip threshold (I_FFT) to provide fast protection against hard short-circuits during steady-state (FET in linear region). After the current exceeds I_FFT, the FET is turned off completely within t_FFT.

The device response after a fast-trip event can be configured using the SC_RETRY bit in the DEVICE_CONFIG register through PMBus® register writes or non-volatile configuration memory. There are 2 programming options available:

1. SC_RETRY = 0 (Default setting): The device latches a fault and remains off till a restart is triggered either externally or through internal auto-retry mechanism as per the RETRY_CONFIG register setting.

   When a short-circuit fault occurs with the SC_RETRY bit in the DEVICE_CONFIG register low, the device:

   • sets the FET_OFF and NONE_OF_THE_ABOVE/UNKNOWN bits in the STATUS_BYTE register

   • sets the OUT_STATUS, PGOODB, and NONE_OF_THE_ABOVE/UNKNOWN bits in the upper byte of the STATUS_WORD register

   • sets the VOUT_UV_WARN bit in the STATUS_OUT register

   • sets the PGOODB and SC_FLT bits in the STATUS_MFR_SPECIFIC_2 register

   • notifies the host by asserting SMBA#, if it is not masked setting the PGOODB and STATUS_OUT bits in the ALERT_MASK register and the GPIO4 pin is configured as SMBA# Output in the GPIO_CONFIG_34 register

   • deasserts the external PG signal, if the GPIO1 pin is configured as PGOOD Output in the GPIO_CONFIG_12 register

   • asserts the FLT signal, if it is not masked setting the SC_FLT bit high in the FAULT_MASK register and the GPIO2 pin is configured as 'FLT Output' in the GPIO_CONFIG_12 register

2. SC_RETRY = 1: The device attempts to turn the FET back ON fully after a short de-glitch interval (30 μs). This allows the FET to try and recover quickly after a transient overcurrent event and minimizes the output voltage droop. However, if the fault is persistent, the device enters current limit causing the junction temperature to rise and eventually enter thermal shutdown. The device latches a fault and remains off till a restart is triggered either externally or through internal auto-retry mechanism as per the RETRY_CONFIG register setting. See Overtemperature Protection section for details on the device response to overtemperature.

   When a short-circuit fault occurs with the SC_RETRY bit in the DEVICE_CONFIG register high, the device:

   • sets the FET_OFF, STATUS_TEMP, and NONE_OF_THE_ABOVE/UNKNOWN bits in the STATUS_BYTE register

   • sets the OUT_STATUS, MFR_STATUS, PGOODB, and NONE_OF_THE_ABOVE/UNKNOWN bits in the upper byte of the STATUS_WORD register

   • sets the VOUT_UV_WARN bit in the STATUS_OUT register

   • sets the OT_FLT bit in the STATUS_TEMP register

   • sets the SOA_FLT bit in the STATUS_MFR_SPECIFIC register

   • sets the PGOODB bit in the STATUS_MFR_SPECIFIC_2 register

   • notifies the host by asserting SMBA#, if it is not masked setting the PGOODB, MFR_STATUS, STATUS_TEMP, and STATUS_OUT bits in the ALERT_MASK register and the GPIO4 pin is configured as SMBA# Output in the GPIO_CONFIG_34 register

   • deasserts the external PG signal, if the GPIO1 pin is configured as PGOOD Output in the GPIO_CONFIG_12 register

   • asserts the FLT signal, if it is not masked setting the SOA_FLT and TEMP_FLT bits high in the FAULT_MASK register and the GPIO2 pin is configured as 'FLT Output' in the GPIO_CONFIG_12 register

Figure 8-5 illustrates the short-circuit response for TPS25990 eFuse.

In some of the systems, for example blade servers and telecom equipment which house multiple hot-pluggable blades or line cards connected to a common supply backplane, there can be transients on the supply due to switching of large currents through the inductive backplane. This can result in current spikes on adjacent cards which can potentially be large enough to trigger the fast-trip comparator of the eFuse. The TPS25990 uses a proprietary algorithm to avoid nuisance tripping in such cases thereby facilitating uninterrupted system operation.

Figure 8-5 Short-Circuit Response