SLVSH67 September   2024 TPS26750

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
      1. 5.1.1 TPS26750 - Absolute Maximum Ratings
      2. 5.1.2 TPS26750 - Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
      1. 5.3.1 TPS26750 - Recommended Operating Conditions
    4. 5.4  Recommended Capacitance
    5. 5.5  Thermal Information
      1. 5.5.1 TPS26750 - Thermal Information
    6. 5.6  Power Supply Characteristics
    7. 5.7  Power Consumption
    8. 5.8  PP_5V Power Switch Characteristics
    9. 5.9  POWER_PATH_EN Characteristics - TPS26750
    10. 5.10 Power Path Supervisory
    11. 5.11 CC Cable Detection Parameters
    12. 5.12 CC VCONN Parameters
    13. 5.13 CC PHY Parameters
    14. 5.14 Thermal Shutdown Characteristics
    15. 5.15 ADC Characteristics
    16. 5.16 Input/Output (I/O) Characteristics
    17. 5.17 BC1.2 Characteristics
    18. 5.18 I2C Requirements and Characteristics
    19. 5.19 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  USB-PD Physical Layer
        1. 7.3.1.1 USB-PD Encoding and Signaling
        2. 7.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 7.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 7.3.1.4 USB-PD BMC Transmitter
        5. 7.3.1.5 USB-PD BMC Receiver
        6. 7.3.1.6 Squelch Receiver
      2. 7.3.2  Power Management
        1. 7.3.2.1 Power-On And Supervisory Functions
        2. 7.3.2.2 VBUS LDO
      3. 7.3.3  Power Paths
        1. 7.3.3.1 Internal Sourcing Power Paths
          1. 7.3.3.1.1 PP_5V Current Clamping
          2. 7.3.3.1.2 PP_5V Local Overtemperature Shut Down (OTSD)
          3. 7.3.3.1.3 PP_5V OVP
          4. 7.3.3.1.4 PP_5V UVLO
          5. 7.3.3.1.5 PP_5Vx Reverse Current Protection
          6. 7.3.3.1.6 PP_CABLE Current Clamp
          7. 7.3.3.1.7 PP_CABLE Local Overtemperature Shut Down (OTSD)
          8. 7.3.3.1.8 PP_CABLE UVLO
      4. 7.3.4  Cable Plug and Orientation Detection
        1. 7.3.4.1 Configured as a Source
        2. 7.3.4.2 Configured as a Sink
        3. 7.3.4.3 Configured as a DRP
        4. 7.3.4.4 Dead Battery Advertisement
      5. 7.3.5  Overvoltage Protection (CC1, CC2)
      6. 7.3.6  Default Behavior Configuration (ADCIN1, ADCIN2)
      7. 7.3.7  ADC
      8. 7.3.8  BC 1.2 (USB_P, USB_N)
      9. 7.3.9  Digital Interfaces
        1. 7.3.9.1 General GPIO
        2. 7.3.9.2 I2C Interface
      10. 7.3.10 Digital Core
      11. 7.3.11 I2C Interface
        1. 7.3.11.1 I2C Interface Description
          1. 7.3.11.1.1 I2C Clock Stretching
          2. 7.3.11.1.2 I2C Address Setting
          3. 7.3.11.1.3 Unique Address Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pin Strapping to Configure Default Behavior
      2. 7.4.2 Power States
    5. 7.5 Thermal Shutdown
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Programmable Power Supply (PPS) - Design Requirements
        2. 8.2.1.2 Liquid Detection Design Requirements
        3. 8.2.1.3 BC1.2 Application Design Requirements
        4. 8.2.1.4 USB Data Support Design Requirements
        5. 8.2.1.5 EPR Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Programmable Power Supply (PPS)
        2. 8.2.2.2 Liquid Detection
        3. 8.2.2.3 BC1.2 Application
        4. 8.2.2.4 USB Data Support
        5. 8.2.2.5 Power Delivery EPR Support
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Programmable Power Supply (PPS) Application Curves
        2. 8.2.3.2 Liquid Detection Application Curves
        3. 8.2.3.3 BC1.2 Application Curves
        4. 8.2.3.4 USB Data Support Application Curves
        5. 8.2.3.5 EPR Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 3.3V Power
        1. 8.3.1.1 VIN_3V3 Input Switch
      2. 8.3.2 1.5V Power
      3. 8.3.3 Recommended Supply Load Capacitance
    4. 8.4 Layout
      1. 8.4.1 TPS26750 - Layout
        1. 8.4.1.1 Layout Guidelines
          1. 8.4.1.1.1 Recommended Via Size
          2. 8.4.1.1.2 Minimum Trace Widths
        2. 8.4.1.2 Layout Example
          1. 8.4.1.2.1 TPS26750 Schematic Layout Example
          2. 8.4.1.2.2 TPS26750 Layout Example - PCB Plots
            1. 8.4.1.2.2.1 TPS26750 Component Placement
            2. 8.4.1.2.2.2 TPS26750 PP5V
            3. 8.4.1.2.2.3 TPS26750 PP_EXT
            4. 8.4.1.2.2.4 TPS26750 VBUS
            5. 8.4.1.2.2.5 TPS26750 I/O
            6. 8.4.1.2.2.6 TPS26750 PPEXT Gate Driver
            7. 8.4.1.2.2.7 TPS26750 GND
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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発注情報

5.18 I2C Requirements and Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I2Ct_IRQ
OD_VOL_IRQ Low level output voltage IOL = 2 mA 0.4 V
OD_LKG_IRQ Leakage Current Output is Hi-Z, VI2Cx_IRQ = 3.45 V –1 1 µA
I2Cc_IRQ
IRQ_VIH High-Level input voltage VLDO_3V3 = 3.3 V 1.3 V
IRQ_VIH_THRESH High-Level input voltage threshold VLDO_3V3 = 3.3 V 0.72 1.3 V
IRQ_VIL low-level input voltage VLDO_3V3 = 3.3 V 0.54 V
IRQ_VIL_THRESH low-level input voltage threshold VLDO_3V3 = 3.3 V 0.54 1.08 V
IRQ_HYS input hysteresis voltage VLDO_3V3 = 3.3 V 0.09 V
IRQ_DEG input deglitch 20 ns
IRQ_ILKG I2Cc_IRQ leakage current VI2Cc_IRQ = 3.45 V –1 1 µA
SDA and SCL Common Characteristics (Controller, Target)
VIL Input low signal VLDO_3V3 = 3.3 V 0.54 V
IOL Max output low current VOL = 0.4 V 15 mA
IOL Max output low current VOL = 0.6 V 20 mA
tf Fall time from 0.7 × VDD to 0.3 × VDD VDD = 1.8 V, 10 pF ≤ Cb ≤ 400 pF 12 80 ns
VDD = 3.3 V, 10 pF ≤ Cb ≤ 400 pF 12 150 ns
tSP I2C pulse width suppressed 50 ns
Cb Capacitive load for each bus line (external) 400 pF
SDA and SCL Standard Mode Characteristics (Target)
fSCLS Clock frequency for target VDD = 1.8 V or 3.3 V 100 kHz
tVD;DAT Valid data time Transmitting Data, VDD = 1.8 V or 3.3 V, SCL low to SDA output valid 3.45 µs
tVD;ACK Valid data time of ACK condition Transmitting Data, VDD = 1.8 V or 3.3 V, ACK signal from SCL low to SDA (out) low 3.45 µs
SDA and SCL Fast Mode Characteristics (Target)
fSCLS Clock frequency for target VDD = 1.8 V or 3.3 V 100 400 kHz
tVD;DAT Valid data time Transmitting data, VDD = 1.8 V, SCL
low to SDA output valid		 0.9 µs
tVD;ACK Valid data time of ACK condition Transmitting data, VDD = 1.8 V or 3.3 V, ACK
signal from SCL low to SDA (out) low		 0.9 µs
fSCLS Clock frequency for Fast Mode Plus(1) VDD = 1.8 V or 3.3 V 400   800 kHz
tVD;DAT Valid data time Transmitting data, VDD = 1.8 V or 3.3 V, SCL
low to SDA output valid		 0.55 µs
tVD;ACK Valid data time of ACK condition Transmitting data, VDD = 1.8 V or 3.3 V, ACK
signal from SCL low to SDA (out) low		 0.55 µs
tLOW Clock low time VDD = 3.3 V 1.3     µs
tHIGH Clock high time VDD = 3.3 V 0.6     µs
(1) Controller must control fSCLS to ensure tLOW > tVD; ACK.