JAJSRQ0A October   2023  – February 2024 TPS274C65CP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Diagrams
      2. 8.3.2 Programmable Current Limit
      3. 8.3.3 Protection Mechanisms
        1. 8.3.3.1 Over-current Protection
        2. 8.3.3.2 Short-Circuit Protection
          1. 8.3.3.2.1 VS During Short-to-Ground
        3. 8.3.3.3 Thermal Shutdown Behavior
        4. 8.3.3.4 Inductive-Load Switching-Off Clamp
        5. 8.3.3.5 Inductive Load Demagnetization
        6. 8.3.3.6 Thermal Shutdown
        7. 8.3.3.7 Undervoltage Protection on VS (UVP)
        8. 8.3.3.8 Undervoltage Lockout on Low Voltage Supply (VDD_UVLO)
        9. 8.3.3.9 Power-Up and Power-Down Behavior
      4. 8.3.4 Diagnostic Mechanisms
        1. 8.3.4.1 Fault Indication
        2. 8.3.4.2 Short-to-Battery and Open-Load Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Off
      2. 8.4.2 Active
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IEC 61000-4-5 Surge
        2. 9.2.2.2 Loss of GND
        3. 9.2.2.3 Paralleling Channels
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.1 Pin Diagrams

This section presents the I/O structure of all digital input and output pins.

GUID-20210824-SS0I-R7DP-QCGC-78JBWQSJM8DG-low.svg
Logic level input pin
Figure 8-1 Logic Level Input PIn
GUID-20210824-SS0I-C3BR-CPQ2-F5HXLK1LB8GT-low.svg
Shows the structure of the open-drain output pin, nFAULT. The open-drain output requires an external pullup resistor to function properly.
Figure 8-2 Open Drain Output Pin (ST)