JAJSRQ0A October   2023  – February 2024 TPS274C65CP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Diagrams
      2. 8.3.2 Programmable Current Limit
      3. 8.3.3 Protection Mechanisms
        1. 8.3.3.1 Over-current Protection
        2. 8.3.3.2 Short-Circuit Protection
          1. 8.3.3.2.1 VS During Short-to-Ground
        3. 8.3.3.3 Thermal Shutdown Behavior
        4. 8.3.3.4 Inductive-Load Switching-Off Clamp
        5. 8.3.3.5 Inductive Load Demagnetization
        6. 8.3.3.6 Thermal Shutdown
        7. 8.3.3.7 Undervoltage Protection on VS (UVP)
        8. 8.3.3.8 Undervoltage Lockout on Low Voltage Supply (VDD_UVLO)
        9. 8.3.3.9 Power-Up and Power-Down Behavior
      4. 8.3.4 Diagnostic Mechanisms
        1. 8.3.4.1 Fault Indication
        2. 8.3.4.2 Short-to-Battery and Open-Load Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Off
      2. 8.4.2 Active
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IEC 61000-4-5 Surge
        2. 9.2.2.2 Loss of GND
        3. 9.2.2.3 Paralleling Channels
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

VVS = 11 V to 36 V, VVDD = 3.0 V to 5.5 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE AND CURRENT
VDS_Clamp CHx VDS clamp voltage  FET current = 10 mA, VS = 24 V 40 44 50 V
VDS_Clamp CHx VDS clamp voltage FET current = 10 mA, VS = 19 V 40 44 50 V
VDS_Clamp CHx VDS clamp voltage FET current = 10 mA, VS = 10 V 33 37 41 V
VS_UVPF VS undervoltage protection falling Measured with respect to the GND pin of the device, All channels ON Output FETs turned off at VS less than this threshold. 8.6 9 9.3 V
VS_UVPR VS undervoltage protection recovery rising Measured with respect to the GND pin of the device, All channels ON Output FETs turned ON at VS more than this threshold. 9.5 10 10.3 V
VS_UVPRH VS undervoltage protection deglitch time Time from triggering the UVP fault to FET turn-off 15 20 25 µs
VS_UVWF VS undervoltage warning falling Measured with respect to the GND pin of the device, 12 12.5 13.5 V
VS_UVWR VS undervoltage warning recovery rising Measured with respect to the GND pin of the device,  11.2 13.5 15.8 V
VS_UVLOF VS  undervoltage lockout falling Measured with respect to the GND pin of the device 3.0 V
VS,UVLOR VS undervoltage lockout rising Measured with respect to the GND pin of the device 2.7 3 3.3 V
VDD,UVLOF VDD  undervoltage lockout falling Measured with respect to the GND pin of the device 2.7 2.8 2.9 V
VDD,UVLOR VDD undervoltage lockout rising Measured with respect to the GND pin of the device 2.8 2.88 2.98 V
ILNOM Continuous load current, per channel All channels enabled, TAMB = 85°C 1.6 A
Two channels enabled, TAMB = 85°C 2.5 A
IOUT,LEAKX Leakage current from OUT to GND in OFF state Vs = VOUT < 36 V, Switch and all diagnostics disabled, measured into the OUTx pin 40 µA
IOUT(OFF) Output leakage current (per channel) VS <= 36 V, VOUT = 0
Channel disabled, diagnostics disabled Tj <= 125°C		 0 0.8 10 µA
VDD IQ VDD quiescent current, all diagnostics disabled, external VDD VS ≤ 36 V, VDD = 5.5 V
All channels enabled,  IOUTx = 0 A		 1.85 2.1 mA
VS IQ VS quiescent current, internal VDD VS ≤ 36 V, 
All channels enabled,  IOUTx = 0 A		 4.9 5.6 mA
VS IQ VS quiescent current, external VDD VS ≤ 36 V, VDD = 3.0 V
All channels enabled,  IOUTx = 0 A		 2.0 2.45 mA
Ileak_LG Leakage current out of the output pins with the GND of IC disconnected, Load ground connected to supply ground VS≤ 30 V, VDD = 5.5 V, RL = 24 Ω
All channels enabled		 0.8 0.9 mA
RON CHARACTERISTICS
RON On-resistance
(Includes MOSFET and package)		 10 V ≤ VS ≤ 36 V, IOUT1 = IOUT2 = 200 mA TJ = 25°C 72 mΩ
TJ = 125°C 110 mΩ
On-resistance when 2 channels are paralleled
(Includes MOSFET and package)		 10 V ≤ VS ≤ 36 V, IOUT1 = IOUT2 > 200 mA.
VOUT1 tied to VOUT2		 TJ = 25°C 33 mΩ
TJ = 125°C 55 mΩ
VDD_REG CHARACTERISTICS
VVDD VDD Output voltage (Internal regulator enabled) 6 V ≤ VS ≤ 36 V, IVDD < 20 mA Includes load and line regulation across the range. 3.1 3.3 3.6 V
LRVDD Load regulation of internal VDD regulator when enabled 6 V ≤ VS ≤ 36 V, IVDD < 20 mA 0.95 V/A
LRtran_VDD Load transient regulation of internal VDD regulator when enabled 6 V ≤ VS ≤ 36 V, IVDD <step from 5 mA to 15 mA in 10 μs 1 uF 10 mV
ICL_VDD Current Limit of internal regulator  6 V ≤ VS ≤ 36 V 25 50 mA
CURRENT LIMIT CHARACTERISTICS
ICLx CHx ICL current limitation level, H version Regulated current at short circuit RL < 200 mohms when Enabled. VDD = 3.3 V. Setting = 2.26 A 2.01 2.26 2.88 A
Setting = 1.9 A 1.6 1.9 2.3 A
Setting = 1.52 A 1.28 1.52 1.76 A
Setting = 1.15 A 0.92 1.15 1.38 A
Settting = 0.86 A 0.74 0.86 0.98 A
Setting = 0.67 A 0.57 0.67 0.77 A
Setting = 0.48 A 0.38 0.48 0.57 A
Setting = 0.29 A 0.22 0.29 0.39 A
ICLx CHx ICL current limitation level Regulated current at short circuit RL < 200 mohms when Enabled. VDD = 3.3 V. Setting = 1.9 A 1.6 1.9 2.3 A
Setting = 1.6 A 1.35 1.6 1.85 A
Setting = 1.25 A 1 1.25 1.5 A
Setting = 1 A 0.85 1 1.15 A
Setting = 0.72 A 0.62 0.72 0.82 A
Setting = 0.56 A 0.47 0.56 0.63 A
Setting = 0.4 A 0.32 0.4 0.47 A
Setting = 0.25 A 0.19 0.25 0.33 A
ICL_PK1 CHx Peak current enabling into permanent short TJ = -40°C to 125°C, VS = 24V Settting = 1.0A 2.80 A
ICL_PK2 CHx Peak current threshold when short is applied while switch enabled TJ = -40°C to 125°C VS = 24V, Minimum inductance = 2.2 uH Settting = 1.0A 8 A
FAULT CHARACTERISTICS
IWB_OFF Off State Wirebreak or Open-load (OL) detection internal pullup current Switch disabled, DIAG_EN = HIGH 38 51 64 µA
VWB_OFF_TH Off state WireBreak (WB) or Open-load (OL) detection voltage Channel Disabled, off-state wire-break diagnostics enabled 5.6 6 6.5 V
TABS Thermal shutdown 160 185 210 °C
THYS Thermal shutdown hysteresis 20 27 35 °C
Vol_FLT Fault low-output voltage IFLT = 2 mA, sink current into the pin 0.4 V
tRETRY Retry time Time from thermal shutdown until switch re-enable. 0.6 ms
DIGITAL INPUT PIN CHARACTERISTIC
VIH, DIG DIG pin Input voltage high-level 3.0 V ≤ VDD ≤ 5.5 V 0.7 × VVDD V
VIL, DIG DIG pin Input voltage low-level 3.0 V ≤ VDD ≤ 5.5 V 0.3 × VVDD V
RREG_EN Internal pullup resistance for REG_EN pin 1 MΩ
RDIGx Internal pulldown resistor 0.7 1 2.0 MΩ
IIH, DIG Input current high-level VDIG = 5 V 5 µA
DIGITAL OUTPUT PIN CHARACTERISTICS
VOL_ST Output Logic Low Voltage  ST Pin current = –4 mA 0.4 V