JAJSN42D December   2011  – December 2021 TPS28225-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout (UVLO)
      2. 7.3.2 Output Active Low
      3. 7.3.3 Enable/Power Good
      4. 7.3.4 3-State Input
      5. 7.3.5 Bootstrap Diode
      6. 7.3.6 Upper and Lower Gate Drivers
      7. 7.3.7 Dead-Time Control
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching the MOSFETs
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Figure 5-1 D Package8-Pin SOICTop View
Figure 5-2 DRB Package8-Pin VSON With Exposed Thermal PadTop View
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
SOIC-8 VSON-8
BOOT 2 2 I Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET.
EN/PG 7 7 I Enable and Power Good input-output pin with 1-MΩ impedance. Connect this pin HIGH to enable and LOW to disable the device. When disabled, the device draws less than
350-μA bias current. If the VDD voltage is below the UVLO threshold or overtemperature shutdown occurs, this pin is internally pulled low.
GND 4 4 GND Ground pin. All signals are referenced to this node.
LGATE 5 5 I Lower gate-drive sink and source output. Connect to the gate of the low-side power N-Channel MOSFET.
PHASE 8 8 I Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin provides a return path for the upper gate driver.
PWM 3 3 — The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see the Section 7.3.4 section for more details. Connect this pin to the PWM output of the controller.
UGATE 1 1 I/O Upper gate-drive sink and source output. Connect to gate of high-side power N-Channel MOSFET.
VDD 6 6 PWR Connect this pin to a 5-V bias supply. Place a high quality bypass capacitor from this pin to GND.
Thermal pad Exposed die pad O Connect directly to GND for better thermal performance and EMI.