SLVS227G August   1999  – June 2024

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings for TPS3123
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Dissipation Rating Table
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Manual Reset ( MR)
      2. 7.3.2 Active-High or Active-Low Output
      3. 7.3.3 Push-Pull or Open-Drain Output
      4. 7.3.4 Watchdog Timer (WDI)
    4. 7.4 Device Functional Modes
  9. 8 Device and Documentation Support
    1. 8.1 Device and Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DBV|5
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

TPS3123-xx TPS3124-xx TPS3125-xx TPS3126-xx TPS3128-xx TPS3123 / TPS3128: DBV PACKAGE5-Pin SOT-23Top ViewFigure 5-1 TPS3123 / TPS3128: DBV PACKAGE
5-Pin SOT-23
Top View
TPS3123-xx TPS3124-xx TPS3125-xx TPS3126-xx TPS3128-xx TPS3125 / TPS3126: DBV PACKAGE5-Pin SOT-23Top ViewFigure 5-3 TPS3125 / TPS3126: DBV PACKAGE
5-Pin SOT-23
Top View
TPS3123-xx TPS3124-xx TPS3125-xx TPS3126-xx TPS3128-xx TPS3124: DBV PACKAGE5-Pin SOT-23Top ViewFigure 5-2 TPS3124: DBV PACKAGE
5-Pin SOT-23
Top View
Table 5-1 Pin Functions
PINI/ODESCRIPTION
PIN NUMBERTPS3123
TPS3128		TPS3124TPS3125
TPS3126
1RESETRESETRESETOActive-Low Output Reset Signal: This pin is driven to a logic low when VDD voltage falls below the negative voltage threshold (VIT-). RESET remains low (asserted) for the delay time period (tD) after VDD voltage rises above VIT+ = VIT- + VHYS.
2GNDGNDGND-GROUND
3MR--IManual Reset: Pull this pin to a logic low to assert a reset signal in the RESET output pin. After MR pin is left floating or pulls to logic high, the RESET output deasserts to the nominal state after the reset delay time (tD) expires.
3-RESETRESETOActive-High Output Reset Signal: This pin is driven to a logic high when VDD voltage falls below the negative voltage threshold (VIT-). RESET remains high (asserted) for the delay time period (tD) after VDD voltage rises above VIT+ = VIT- + VHYS.
4WDIWDIMRIWatchdog Timer Input: If WDI remains high or low longer than the timeout period, then reset is triggered. The timer clears when reset is asserted or when WDI sees a rising edge or a falling edge.
5VDDVDDVDDIInput Supply Voltage: Supply voltage pin. Good analog design practice is to place a 0.1µF ceramic capacitor close to this pin.