SLVS227G August   1999  – June 2024

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings for TPS3123
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Dissipation Rating Table
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Manual Reset ( MR)
      2. 7.3.2 Active-High or Active-Low Output
      3. 7.3.3 Push-Pull or Open-Drain Output
      4. 7.3.4 Watchdog Timer (WDI)
    4. 7.4 Device Functional Modes
  9. 8 Device and Documentation Support
    1. 8.1 Device and Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DBV|5
サーマルパッド・メカニカル・データ
発注情報

6.7 Switching Characteristics

at RL = 1MΩ, CL = 50pF, TA = +25°C.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
ttoutWatchdog time outVDD ≥ VIT– + 0.2V,
See timing diagram		0.81.42.1s
tdDelay timeVDD > VIT– + 0.2V,
See timing diagram		100180260ms
tPHLPropagation delay time, high-to-low-level outputMR to RESET delay (TPS3123/5/6/8)VDD ≥ VIT–+ 0.2V,
VIL = 0.2 × VDD,
VIH = 0.8 × VDD		0.1μs
tPLHPropagation delay time, low-to-high-level outputMR to RESET delay (TPS3125/6)0.1
tPHLPropagation delay time, high-to-low-level outputVDD to RESET delayVIL = VIT– – 0.2V,
VIH = VIT– + 0.2V		10μs
tPLHPropagation delay time, low-to-high-level outputVDD to RESET delay (TPS3124/5/6)10