SBVS211B August   2012  – April 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Push-Button Timer Selection (TS)
      2. 7.3.2 Inputs
        1. 7.3.2.1 TPS3420 Inputs (PB1, PB2)
        2. 7.3.2.2 TPS3421 Inputs (PB1, PB2)
        3. 7.3.2.3 TPS3422 Inputs (PB1)
      3. 7.3.3 Output (RST)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > 1.6 V)
      2. 7.4.2 Below VDD(min) (1.6 V > VDD > 1.3 V)
      3. 7.4.3 Power-On Reset (VDD < 1.3 V)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Single Input With Fixed Reset Pulse Duration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Dual Input Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
      3. 8.2.3 Latched Reset Signal
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Voltage VCC –0.3 7 V
RST –0.3 7
PB1, PB2 –0.3 7
TS –0.3 VCC + 0.3
Current RST pin –20 20 mA
Temperature(2) Operating junction, TJ –40 125 °C
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Input supply voltage 1.6 6.5 V
VTS TS pin voltage 0 VCC V
VPB1, VPB2 PB1 and PB2 pin voltage 0 6.5 V
VRST RST pin voltage 0 6.5 V
IRST RST pin current 0.00035 8 mA

6.4 Thermal Information

THERMAL METRIC(1) TPS342x UNIT
DRY (USON)
6 PINS
RθJA Junction-to-ambient thermal resistance 322 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 1185.2
RθJB Junction-to-board thermal resistance 184.7
ψJT Junction-to-top characterization parameter 34.9
ψJB Junction-to-board characterization parameter 182.6
RθJC(bot) Junction-to-case (bottom) thermal resistance 69.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

All specifications are over the operating temperature range of –40°C < TJ < 125°C and 1.6 V ≤ VCC ≤ 6.5 V, unless otherwise noted. Typical values are at TJ = 25°C and VCC = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC Input supply 1.6 6.5 V
ICC Supply current (standby) TPS3421, TPS3422 VCC = 3.3 V 250 nA
VCC = 6.5 V, –40°C < TJ < 85°C 1 µA
VCC = 6.5 V 3.3 µA
TPS3420 VCC = 3.3 V 350 nA
VCC = 6.5 V, –40°C < TJ < 85°C 1.2 µA
VCC = 6.5 V 3.4 µA
Supply current (active timer)(1) TPS3420, TPS3421 PB1, PB2 = 0 V, VCC = 6.5 V 6 12 µA
TPS3422 PB1, PB2 = 0 V, VCC = 6.5 V 106 136
VIH High-level input voltage TPS3421, TPS3422 PB1, PB2 0.7 VCC V
TPS3420 PB1, PB2 0.85
VIL Low-level input voltage TPS3421, TPS3422 PB1, PB2 0 0.3 VCC V
TPS3420 PB1, PB2 0 0.3
RPB1 PB1 internal pullup resistance (TPS3422) 65 kΩ
IPB Input current (PB1, PB2) TPS3420 TPS3421 PB1, PB2 = 0 V or VCC –50 50 nA
TPS3422 PB1, PB2 = VCC –50 50
VOL Low-level output voltage VCC ≥ 4.5 V, ISINK = 8 mA 0.4 V
VCC ≥ 3.3 V, ISINK = 5 mA 0.3
VCC ≥ 1.6 V, ISINK = 3 mA 0.3
Ilkg(OD) Open-drain output leakage current High impedance, VRST = 6.5 V –0.35 0.35 µA
(1) Includes current through pullup resistor between input pin (PB1) and supply pin (VCC) for TPS3422.

6.6 Timing Requirements

All specifications are over the operating temperature range of –40°C < TJ < 125°C and 1.6 V ≤ VCC ≤ 6.5 V, unless otherwise noted. Typical values are at TJ = 25°C and VCC = 3.3 V.
MIN TYP MAX UNIT
tTIMER Push-button timer(1) –20% 20%
TPS3420D: TS = GND 6 7.5 9 s
TPS3420D: TS = VCC 10 12.5 15
TPS3421Ey, TPS3422Ey: TS = GND 6 7.5 9
TPS3421Ey, TPS3422Ey: TS = VCC 0
tRST Reset pulse duration –20% 20%
TPS3421xC 64 80 96 ms
TPS3421xG 320 400 480
TPS3422xG 320 400 480
tDD Detection delay (from input to RST)(2) For 0-s tTIMER condition 150 µs
tSD Start-up delay(2) VCC rising 300 µs
(1) For devices with a 0-second delay while TS = VCC, this option is only for factory testing and is not intended for normal operation. In normal operation, the TS pin should be tied to GND.
(2) For devices with a 0-second delay when TS = VCC, reset asserts in tDD time when both PB inputs go low in this configuration. During start-up, if the PB inputs are low, reset asserts after a start-up time delay. This value is specified by design.
TPS342 tim_tps3420_bvs211.gif
1. For the TPS3420, tRST is not a fixed time, but instead depends on one of the PB pins going high.
Figure 1. TPS3420 Timing Diagram
TPS342 tim_bvs211.gifFigure 2. TPS3421 Timing Diagram
TPS342 tim_tps3422_bvs211.gifFigure 3. TPS3422 Timing Diagram

6.7 Typical Characteristics

At TJ = 25°C and VCC = 3.3 V, unless otherwise noted.
TPS342 C001_BVS211.png
Figure 4. TPS3421: Standby Supply Current vs Supply Voltage
TPS342 C003_BVS211.png
TS = GND
Figure 6. Push-Button Timer vs Temperature
TPS342 C005_BVS211.png
VCC = 1.6 V
Figure 8. Output Voltage Low vs Output Sink Current
TPS342 C007_BVS211.png
VCC = 6.5 V
Figure 10. Output Voltage Low vs Output Sink Current
TPS342 C002_BVS211.png
PB1 = PB2 = GND
Figure 5. TPS3421: Active Supply Current vs Supply Voltage
TPS342 C004_BVS211.png
Figure 7. Reset Pulse Duration vs Temperature
TPS342 C006_BVS211.png
VCC = 3.3 V
Figure 9. Output Voltage Low vs Output Sink Current