JAJSFU0A
July 2018 – October 2021
TPS3430
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Timing Diagrams
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagrams
7.3
Feature Description
7.3.1
CRST
7.3.2
Window Watchdog
7.3.2.1
SET0 and SET1
7.3.2.1.1
Enabling the Window Watchdog
7.3.2.1.2
Disabling the Watchdog Timer When Using the CRST Capacitor
7.3.2.1.3
SET0 and SET1 During Normal Watchdog Operation
7.3.3
Window Watchdog Timer
7.3.3.1
CWD
7.3.3.2
WDI Functionality
7.3.3.3
WDO Functionality
7.4
Device Functional Modes
7.4.1
VDD is Below VPOR ( VDD < VPOR)
7.4.2
VDD is Above VPOR And Below VDD (min)( VPOR < VDD < VDD (min))
7.4.3
Normal Operation (VDD ≥ VDD (min))
8
Application and Implementation
8.1
Application Information
8.1.1
CRST Delay
8.1.1.1
Factory-Programmed Watchdog Reset Delay Timing
8.1.1.2
CRST Programmable Watchdog Reset Delay
8.1.2
CWD Functionality
8.1.2.1
Factory-Programmed Timing Options
8.1.2.2
CWD Adjustable Capacitor Watchdog Timeout
8.2
Typical Applications
8.2.1
Monitoring Microcontroller with Watchdog Timer - Design 1
8.2.1.1
Design Requirements - Design 1
8.2.1.2
Detailed Design Procedure - Design 1
8.2.1.2.1
Meeting the Minimum Watchdog Reset Delay - Design 1
8.2.1.2.2
Setting the Watchdog Window - Design 1
8.2.1.2.3
Calculating the WDO Pull-up Resistor - Design 1
8.2.2
Monitoring Microcontroller with a Programmed Window Watchdog Timer - Design 2
8.2.2.1
Design Requirements - Design 2
8.2.2.2
Detailed Design Procedure - Design 2
8.2.2.2.1
Meeting the Minimum Watchdog Reset Delay - Design 2
8.2.2.2.2
Setting the Watchdog Window - Design 2
8.2.2.2.3
Calculating the WDO Pull-up Resistor - Design 2
8.2.3
Monitoring Microcontroller with a Latching Window Watchdog Timer - Design 3
8.2.3.1
Design Requirements - Design 3
8.2.3.2
Detailed Design Procedure - Design 3
8.2.3.2.1
Meeting the Latching Output Requirement - Design 3
8.2.3.2.2
Setting the Watchdog Window - Design 3
8.2.3.3
Application Curve - Design 3
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Receiving Notification of Documentation Updates
11.4
サポート・リソース
11.5
Trademarks
11.6
Electrostatic Discharge Caution
11.7
Glossary
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DRC|10
MPDS117L
サーマルパッド・メカニカル・データ
DRC|10
QFND013N
発注情報
jajsfu0a_oa
jajsfu0a_pm
7.2
Functional Block Diagrams
VDD1 and VDD2 are not internally connected and must be connected externally for the device to function.
Figure 7-1
TPS3430 Block Diagram