JAJSFT7A July   2018  – October 2021 TPS3431

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable Input (EN) and Enable Output (ENOUT)
      2. 7.3.2 Watchdog Mode
        1. 7.3.2.1 CWD
        2. 7.3.2.2 Watchdog Input WDI
        3. 7.3.2.3 Watchdog Output WDO
        4. 7.3.2.4 SET1
    4. 7.4 Device Functional Modes
      1. 7.4.1 VDD is Below VPOR ( VDD < VPOR)
      2. 7.4.2 Above Power-On-Reset, But Less Than VDD(min) (VPOR ≤ VDD < VDD(min))
      3. 7.4.3 Normal Operation (VDD ≥ VDD(min))
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 CWD Functionality
        1. 8.1.1.1 Factory-Programmed Timing Options
        2. 8.1.1.2 CWD Adjustable Capacitor Watchdog Timeout
    2. 8.2 Typical Application
      1. 8.2.1 Design 1 Requirements
      2. 8.2.2 Detailed Design 1 Procedure
        1. 8.2.2.1 Calculating WDO Pullup Resistor Design 1
        2. 8.2.2.2 Setting the Watchdog Design 1
      3. 8.2.3 Application Curves Design 1
    3. 8.3 Programmable Application
      1. 8.3.1 Design 2 Requirements
      2. 8.3.2 Detailed Design 2 Procedure
        1. 8.3.2.1 Calculating WDO Pullup Resistor Design 2
        2. 8.3.2.2 Setting the Watchdog Design 2
        3. 8.3.2.3 Watchdog Disabled During Initialization Period Design 2
        4. 8.3.2.4 Programmable Disable Feature Design 2
      3. 8.3.3 Application Curves Design 2
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.1.2 CWD Adjustable Capacitor Watchdog Timeout

Adjustable capacitor timing is achievable by connecting a capacitor to the CWD pin. If a capacitor is connected to CWD, then a 375-nA, constant-current source charges CCWD until VCWD = 1.21 V. Table 8-2 shows how to calculate tWD using Equation 1 and the SET1 pin. The TPS3431 determines the watchdog timeout with the formulas given in Equation 1, where CCWD is in nanofarads and tWD is in milliseconds.

Equation 1. tWD(ms) = 77.4 x CCWD(nF) + 55 (ms)

The TPS3431 is designed and tested using CCWD capacitors between 100 pF and 1 µF. Note that Equation 1 is for ideal capacitors and capacitor tolerances vary the actual device timing. For the most accurate timing, use ceramic capacitors with COG dielectric material. If a CCWD capacitor is used, Equation 1 can be used to set tWD for the watchdog timeout. Table 8-3 shows the minimum and maximum calculated tWD values using an ideal capacitor.

Table 8-2 Programmable CWD Timing
INPUTWATCHDOG TIMEOUT WDT (tWD)(1)UNIT
CWDSET1MINTYPMAX
CCWD0Watchdog disabled
CCWD1tWD × 0.905tWD Equation 1tWD × 1.095ms
(1) Calculated from Equation 1 using an ideal capacitor.
Table 8-3 tWD Values for Common Ideal Capacitor Values
CCWDWATCHDOG TIMEOUT WDT (tWD)UNIT
MIN(1)TYPMAX(1)
100 pF56.7762.7468.7ms
1 nF119.82132.4144.98ms
10 nF750829908ms
100 nF705477958536ms
1 μF700967745584814ms
(1) The minimum and maximum values are calculated using an ideal capacitor.