JAJSKP2E august   2020  – august 2023 TPS37-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 8.3.1.2 Power-On Reset (VDD < VPOR )
      2. 8.3.2 SENSE
        1. 8.3.2.1 SENSE Hysteresis
      3. 8.3.3 Output Logic Configurations
        1. 8.3.3.1 Open-Drain
        2. 8.3.3.2 Push-Pull
        3. 8.3.3.3 Active-High (RESET)
        4. 8.3.3.4 Active-Low (RESET)
      4. 8.3.4 User-Programmable Reset Time Delay
        1. 8.3.4.1 Reset Time Delay Configuration
      5. 8.3.5 User-Programmable Sense Delay
        1. 8.3.5.1 Sense Time Delay Configuration
      6. 8.3.6 Manual RESET (CTR1 / MR) and (CTR2 / MR) Input
  10. 9 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Adjustable Voltage Thresholds
    2. 10.2 Application Information
    3. 10.3 Typical Application
      1. 10.3.1 Design 1: Automotive Off-Battery Monitoring
        1. 10.3.1.1 Design Requirements
        2. 10.3.1.2 Detailed Design Procedure
        3. 10.3.1.3 Application Curves
    4. 10.4 Power Supply Recommendations
      1. 10.4.1 Power Dissipation and Device Operation
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
      3. 10.5.3 Creepage Distance
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.1.2 Power-On Reset (VDD < VPOR )

When the voltage on VDD is lower than the power on reset voltage (VPOR), the output signal is undefined and is not to be relied upon for proper device function.

GUID-20210103-CA0I-KH6T-CL2B-5DJ0FRDLVC77-low.svg Figure 8-2 Power Cycle (SENSE Outside of Nominal voltage) (2)
GUID-20210103-CA0I-B5XD-BPK4-LHPTTLMQQCKB-low.svg Figure 8-3 Power Cycle (SENSE Within Nominal voltage) (3)
2. Figure assumes an external pull-up resistor is connected to the reset pin via VDD
3. Figure assumes an external pull-up resistor is connected to the reset pin via VDD