JAJSK37E october   2020  – august 2023 TPS37

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 8.3.1.2 Power-On Reset (VDD < VPOR )
      2. 8.3.2 SENSE
        1. 8.3.2.1 SENSE Hysteresis
      3. 8.3.3 Output Logic Configurations
        1. 8.3.3.1 Open-Drain
        2. 8.3.3.2 Push-Pull
        3. 8.3.3.3 Active-High (RESET)
        4. 8.3.3.4 Active-Low (RESET)
      4. 8.3.4 User-Programmable Reset Time Delay
        1. 8.3.4.1 Reset Time Delay Configuration
      5. 8.3.5 User-Programmable Sense Delay
        1. 8.3.5.1 Sense Time Delay Configuration
      6. 8.3.6 Manual RESET (CTR1 / MR) and (CTR2 / MR) Input
  10. 9 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Adjustable Voltage Thresholds
      1. 10.1.1 Application Curves
    2. 10.2 Application Information
      1. 10.2.1 Typical Application
        1. 10.2.1.1 Design 1: High Voltage – Fast AC Signal Monitoring For Power Fault Detection
          1. 10.2.1.1.1 Design Requirements
          2. 10.2.1.1.2 Detailed Design Procedure
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Power Dissipation and Device Operation
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
      3. 10.4.3 Creepage Distance
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

At VDD(MIN) ≤ VDD ≤ VDD(MAX), CTR1/MR = CTR2/MR = CTS1 = CTS2 = open, output reset pull-up resistor RPU = 10 kΩ, voltage VPU = 5.5 V, and load CLOAD = 10 pF. The operating free-air temperature range TA = – 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C and VDD = 16 V and VIT = 6.5 V (VIT refers to VITN or VITP).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD
VDD Supply Voltage 2.7 65 V
UVLO (1) Undervoltage Lockout VDD Falling below VDD (MIN) 2.7 V
VPOR Power on Reset Voltage (2)
RESET, Active Low
(Open-Drain, Push-Pull )		 VOL(MAX) = 300 mV
IOUT (Sink) = 15 µA
 1.4 V
VPOR Power on Reset Voltage (2)
RESET, Active High
(Push-Pull )		 VOH(MIN) = 0.8 x VDD
IOUT (Source) = 15 µA
 1.4 V
IDD Supply current into VDD pin VIT = 800 mV
VDD (MIN) ≤ VDD ≤ VDD (MAX)
 1 2.6 µA
VIT = 2.7 V to 36 V
VDD (MIN) ≤ VDD ≤ VDD (MAX)
 1 2 µA
SENSE (Input)
ISENSE Input current                        (SENSE1, SENSE2)
VIT = 800 mV
 100 nA
ISENSE Input current                        (SENSE1, SENSE2)
VIT < 10 V

 		 0.8 µA
ISENSE Input current                        (SENSE1, SENSE2)
10 V < VIT < 26 V

 		 1.2 µA
ISENSE Input current                        (SENSE1, SENSE2)
VIT > 26 V

 		 2 µA
VITN  Input Threshold Negative
(Undervoltage)		 VIT = 2.7 V to 36 V -1.5 1.5 %
VIT = 800 mV (3) 0.792 0.800 0.808 V
VITP
Input Threshold Positive 
(Overvoltage)
 		 VIT = 2.7 V to 36 V -1.5 1.5 %
VIT = 800 mV (3) 0.792 0.800 0.808 V
VHYS Hysteresis  Accuracy (4) VIT = 0.8 V and 2.7 V to 36 V
VHYS Range = 2% to 13% (1% step)		 -1.5 1.5 %
VIT = 2.7 V to 8 V
VHYS = 0.5 V, 1 V, 1.5 V, 2 V, 2.5 V
(VITP - VHYS) ≥ 2.4 V, OV Only		 -1.5 1.5 %
RESET (Output)
Ilkg(OD) Open-Drain leakage 
(RESET1, RESET2)		 VRESET = 5.5 V
VITN < VSENSE < VITP		 300 nA

VRESET = 65 V
VITN < VSENSE < VITP		 300 nA
VOL (5) Low level output voltage 2.7 V ≤ VDD ≤ 65 V
IRESET = 5 mA
 300 mV
VOH_DO High level output voltage dropout 
(VDD - VOH = VOH_DO)
(Push-Pull only)
 		 2.7 V ≤ VDD ≤ 65 V
IRESET = 500 uA
 100 mV
VOH (5) High level output voltage
(Push-Pull only)
 		 2.7 V ≤ VDD ≤ 65 V
IRESET = 5 mA
 0.8VDD V
Capacitor Timing (CTS, CTR)
RCTR Internal resistance (CTR1 / MR , CTR2 / MR ) 877 1000 1147 Kohms
RCTS Internal resistance                (CTS1, CTS2)    88 100 122 Kohms
Manual Reset (MR)
VMR_IH CTR1 / MR and CTR2 / MR pin                      logic high input VDD = 2.7 V 2200 mV
VMR_IH CTR1 / MR and CTR2 / MR pin                      logic high input VDD = 65 V 2500 mV
VMR_IL  CTR1 / MR and CTR2 / MR pin                      logic low input VDD = 2.7 V 1300 mV
VMR_IL  CTR1 / MR and CTR2 / MR pin                      logic low input VDD = 65 V 1300 mV
(1) When VDD voltage falls below UVLO, reset is asserted for Output 1 and Output 2. VDD slew rate ≤ 100 mV / µs
(2) VPOR is the minimum VDD voltage for a controlled output state. Below VPOR, the output cannot be determined. VDD dv/dt ≤ 100mV/µs
(3) For adjustable voltage guidelines and resistor selection refer to Adjustable Voltage Thresholds in Application and Implementation section
(4) Hysteresis is with respect to VITP and VITN voltage threshold. VITP has negative hysteresis and VITN has positive hysteresis.
(5) For VOH and VOL relation to output variants refer to Timing Figures after the Timing Requirement Table