JAJSQ83F november   1998  – october 2020

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics for TPS3705-33 Only
    7. 7.7  Timing Requirements
    8. 7.8  Switching Characteristics
    9. 7.9  Dissipation Ratings
    10. 7.10 Timing Diagram
    11. 7.11 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Manual Reset Input
      2. 8.3.2 Power-Fail Comparator
      3. 8.3.3 Watchdog Timer
    4. 8.4 Device Functional Modes
      1. 8.4.1 VDD < 1.1 V
      2. 8.4.2 1.1 V < VDD ≤ 2 V
      3. 8.4.3 2 V < VDD < 6 V
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage TPS370x-xx, VDD = 1.1 V, IOH = –4 μA 0.8 V
TPS3707-25, TPS370x-30, TPS370x-33,
VDD = VIT+ + 0.2 V, IOH = –500 μA		 0.7 × VDD
TPS370x-50, VDD = VIT+ + 0.2 V, IOH = –800 μA VDD – 1.5
TPS370x-xx, VDD = 6 V, IOH = –800 μA VDD – 1.5
VOL Low-level output voltage TPS3707-25, TPS370x-30, TPS370x-33,
VDD = VIT+ + 0.2 V, IOL = 1 mA		 0.3 V
TPS370x-50, VDD = VIT+ + 0.2 V, IOL = 2.5 mA 0.4
TPS370x-xx, VDD = 6 V, IOL = 3 mA 0.4
Power-up reset voltage(1) VDD ≥ 1.1 V, IOL = 50 μA 0.3 V
VIT– Negative-going input
threshold voltage(2)		 TPS3707-25, TA = 0°C to 85°C 2.2 2.25 2.3 V
TPS370x-30, TA = 0°C to 85°C 2.57 2.63 2.68
TPS370x-33, TA = 0°C to 85°C 2.87 2.93 2.98
TPS370x-50, TA = 0°C to 85°C 4.45 4.55 4.63
TPS3707-25, TA = –40°C to 85°C 2.2 2.25 2.32
TPS370x-30, TA = –40°C to 85°C 2.57 2.63 2.7
TPS370x-33, TA = –40°C to 85°C 2.87 2.93 3
TPS370x-50, TA = –40°C to 85°C 4.45 4.55 4.65
Negative-going input
threshold voltage, PFI(2)		 TPS370x-xx, VDD ≥ 2 V, TA = –40°C to 85°C 1.2 1.25 1.3
Vhys Hysteresis, VDD TPS3707-25 40 mV
TPS370x-30 50
TPS370x-33 50
TPS370x-50 70
Hysteresis, PFI TPS370x-xx 10
IIH(AV) Average high-level input current, WDI WDI = VDD = 6 V, time average (dc = 88%) 100 150 µA
IIL(AV) Average low-level input current, WDI WDI = 0 V, VDD = 6 V, time average (dc = 12%) –15 –20 µA
IIH High-level input current, WDI WDI = VDD = 6 V 120 170 µA
High-level input current, MR MR = 0.7 × VDD, VDD = 6 V –130 –180
IIL Low-level input current, WDI WDI = 0 V, VDD = 6 V –120 –170 µA
Low-level input current, MR MR = 0 V, VDD = 6 V –430 –600
II Input current, PFI VDD = 6 V, 0 V ≤ VI ≤ VDD –1 0 1 µA
IDD Supply current TPS3705-xx, VDD = 2 V to 6 V, MR = VDD,
MR, WDI and outputs unconnected		 30 50 µA
TPS3707-xx, VDD = 2 V to 6 V, MR = VDD,
MR, WDI and outputs unconnected		 20 50
Ci Input capacitance VI = 0 V to VDD 5 pF
(1) The lowest supply voltage at which RESET becomes active, tr,VDD ≥ 15 µs/V
(2) To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near to the supply terminals