JAJSQ83F november   1998  – october 2020

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics for TPS3705-33 Only
    7. 7.7  Timing Requirements
    8. 7.8  Switching Characteristics
    9. 7.9  Dissipation Ratings
    10. 7.10 Timing Diagram
    11. 7.11 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Manual Reset Input
      2. 8.3.2 Power-Fail Comparator
      3. 8.3.3 Watchdog Timer
    4. 8.4 Device Functional Modes
      1. 8.4.1 VDD < 1.1 V
      2. 8.4.2 1.1 V < VDD ≤ 2 V
      3. 8.4.3 2 V < VDD < 6 V
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.3 2 V < VDD < 6 V

When VDD is greater than 2 V but less than 6 V, the device is within the recommended operating conditions (see Section 7.3). See Table 8-1, Table 8-2, and Table 8-3 for corresponding truth tables.

Table 8-1 TPS3705 Truth Table
MR VDD > VIT RESET TYPICAL DELAY
H → L 1 H → L 30 ns
L → H 1 L → H 200 ms
H 1 → 0 H → L 3 µs
H 0 → 1 L → H 200 ms
Table 8-2 TPS3707 Truth Table
MR VDD > VIT RESET RESET TYPICAL DELAY
H → L 1 H → L L → H 30 ns
L → H 1 L → H H → L 200 ms
H 1 → 0 H → L L → H 3 µs
H 0 → 1 L → H H → L 200 ms
Table 8-3 TPS370x Truth Table
PFI > VIT PFO TYPICAL DELAY
0 → 1 L → H 0.5 µs
1 → 0 H → L 0.5 µs