JAJSQ83F november   1998  – october 2020

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics for TPS3705-33 Only
    7. 7.7  Timing Requirements
    8. 7.8  Switching Characteristics
    9. 7.9  Dissipation Ratings
    10. 7.10 Timing Diagram
    11. 7.11 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Manual Reset Input
      2. 8.3.2 Power-Fail Comparator
      3. 8.3.3 Watchdog Timer
    4. 8.4 Device Functional Modes
      1. 8.4.1 VDD < 1.1 V
      2. 8.4.2 1.1 V < VDD ≤ 2 V
      3. 8.4.3 2 V < VDD < 6 V
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.8 Switching Characteristics

at RL = 1 MΩ, CL = 50 pF, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tt(out) Watchdog time out VDD ≥ VIT+ + 0.2 V, see Figure 7-1 1.1 1.6 2.3 s
td Delay time VDD ≥ VIT+ + 0.2 V, see Figure 7-1 140 200 280 ms
tPHL Propagation (delay) time,
high-to-low-level output		 MR to RESET delay, VDD ≥ VIT+ + 0.2 V,
VIL = 0.3 × VDD, VIH = 0.7 × VDD		 50 250 ns
tPLH Propagation (delay) time,
low-to-high-level output		 MR to RESET delay (TPS3707-xx only)
VDD ≥ VIT+ + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD		 50 250 ns
tPHL Propagation (delay) time,
high-to-low-level output		 VDD to RESET delay 3 5 µs
tPLH Propagation (delay) time,
low-to-high-level output		 VDD to RESET delay (TPS3707-xx only) 3 5 µs
tPHL Propagation (delay) time,
high-to-low-level output		 PFI to PFO delay, VDD = 2 V to 6 V 0.5 1 µs
tPLH Propagation (delay) time,
low-to-high-level output		 PFI to PFO delay, VDD = 2 V to 6 V 0.5 1 µs