JAJST93A October   2015  – February 2024 TPS3710

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input (SENSE)
      2. 6.3.2 Output (OUT)
      3. 6.3.3 Immunity to Input-Pin Voltage Transients
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation (VDD > UVLO)
      2. 6.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
      3. 6.4.3 Power-On Reset (VDD < V(POR))
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 VPULLUP to a Voltage Other Than VDD
      2. 7.1.2 Monitoring VDD
      3. 7.1.3 Monitoring a Voltage Other Than VDD
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Resistor Divider Selection
        2. 7.2.2.2 Pullup Resistor Selection
        3. 7.2.2.3 Input Supply Capacitor
        4. 7.2.2.4 Sense Capacitor
      3. 7.2.3 Application Curve
    3. 7.3 Do's and Don'ts
    4. 7.4 Power-Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

GUID-C4C6D655-C172-41F4-8672-CC1EEF674D71-low.gif Figure 4-1 DDC Package
6-Pin SOT
Top View
GUID-7891EF16-CCE2-41D1-9F18-62534B6EC5A1-low.gif Figure 4-2 DSE Package
6-Pin WSON
Top View
Table 4-1 Pin Functions
PIN I/O DESCRIPTION
NAME DDC DSE
GND 2, 4, 6 1, 3, 5 — Connect all three pins to ground.
OUT 1 6 O SENSE comparator open-drain output. OUT is driven low when the voltage at this comparator is below (VIT-). The output goes high when the sense voltage returns above the respective threshold (VIT+).
SENSE 3 4 I This pin is connected to the voltage to be monitored with the use of an external resistor divider. When the voltage at this pin drops below the threshold voltage (VIT-), OUT is driven low.
VDD 5 2 I Supply voltage input. Connect a 1.8V to 18V supply to VDD to power the device. Good analog design practice is to place a 0.1µF ceramic capacitor close to this pin.