SNVSCN2 September   2024 TPS37100-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 7.3.1.2 Power-On Reset (VDD < VPOR )
      2. 7.3.2 SENSE
        1. 7.3.2.1 Adjustable Voltage Thresholds
        2. 7.3.2.2 SENSE Hysteresis
        3. 7.3.2.3 Reverse Polarity Protection
      3. 7.3.3 Output Logic Configurations
        1. 7.3.3.1 Open-Drain
        2. 7.3.3.2 Active-Low (OUT A and OUT B)
        3. 7.3.3.3 Latching
      4. 7.3.4 User-Programmable Release Time Delay
        1. 7.3.4.1 Deassertion Time Delay Configuration
      5. 7.3.5 User-Programmable Sense Delay
        1. 7.3.5.1 Sense Time Delay Configuration
      6. 7.3.6 Analog Out
      7. 7.3.7 Built-in Self-Test
        1. 7.3.7.1 Latching
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design 1: Off-Battery Monitoring
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Dissipation and Device Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Creepage Distance
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

3 Description

The TPS37100-Q1 and TPS37102-Q1 are 105V input voltage supervisors with low quiescent current (5uA), fast detection time, and an integrated buffer for supply voltage measurements. This family of devices can be connected directly to a 24V / 48V / 52V battery or voltage rail for continuous monitoring of over (OV) or under (UV) voltage conditions. Wide hysteresis voltage options are available to ignore false output deassertions that are be caused by battery voltage transients.

The TPS37100-Q1 and TPS37102-Q1 include two outputs (OUT A and OUT) that are used as separate OV and UV fault monitors enabling system to take different action based on the fault that occurs. Additionally, the AOUT pin provides a scaled down SENSE pin voltage output and is intended to be sampled by ADC for supply voltage measurements. The user can choose the scaling factor desired based on the orderable part selected. The TPS37102-Q1 comes with BIST which is implemented at start-up to verify device health as well as an optional latching feature on OUT A to help the system bring into a safe state when critical faults occurs.

Device Information
PART NUMBERPACKAGE (1)BODY SIZE (NOM) (3)
TPS37100-Q1SOT-23 (14) (DYY)4.1mm × 1.9mm
TPS37102-Q1(2)SOT-23 (14) (DYY)4.1mm × 1.9mm
(1) For package details, see the mechanical drawing addendum at the end of the data sheet.
(2) PRODUCT PREVIEW
(3) The package size (length × width) is a nominal value and includes pins, where applicable.
TPS37100-Q1 TPS37102-Q1 Typical Application CircuitTypical Application Circuit
TPS37100-Q1 TPS37102-Q1 Typical IDD vs Temperature (VDD = 48V)Typical IDD vs Temperature (VDD = 48V)