JAJSVT4 September   2024 TPS37100-Q1

ADVANCE INFORMATION  

1.   1
2. 1 特長
3. 2 アプリケーション
4. 3 概要
5. 4 Device Comparison
6. 5 Pin Configuration and Functions
7. 6 Specifications
   1. 6.1 Absolute Maximum Ratings
   2. 6.2 ESD Ratings
   3. 6.3 Recommended Operating Conditions
   4. 6.4 Thermal Information
   5. 6.5 Electrical Characteristics
   6. 6.6 Switching Characteristics
   7. 6.7 Timing Requirements
   8. 6.8 Timing Diagrams
   9. 6.9 Typical Characteristics
8. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
         1. 7.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
         2. 7.3.1.2 Power-On Reset (VDD < VPOR )
      2. 7.3.2 SENSE
         1. 7.3.2.1 Adjustable Voltage Thresholds
         2. 7.3.2.2 SENSE Hysteresis
         3. 7.3.2.3 Reverse Polarity Protection
      3. 7.3.3 Output Logic Configurations
         1. 7.3.3.1 Open-Drain
         2. 7.3.3.2 Active-Low (OUT A and OUT B)
         3. 7.3.3.3 Latching
      4. 7.3.4 User-Programmable Release Time Delay
         1. 7.3.4.1 Deassertion Time Delay Configuration
      5. 7.3.5 User-Programmable Sense Delay
         1. 7.3.5.1 Sense Time Delay Configuration
      6. 7.3.6 Analog Out
      7. 7.3.7 Built-in Self-Test
         1. 7.3.7.1 Latching
9. 8 Application and Implementation
   1. 8.1 Application Information
   2. 8.2 Typical Application
      1. 8.2.1 Design 1: Off-Battery Monitoring
         1. 8.2.1.1 Design Requirements
         2. 8.2.1.2 Detailed Design Procedure
         3. 8.2.1.3 Application Curves
   3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Dissipation and Device Operation
   4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Creepage Distance
10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
11. 10Revision History
12. 11Mechanical, Packaging, and Orderable Information