SNVSCN2 September   2024 TPS37100-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 7.3.1.2 Power-On Reset (VDD < VPOR )
      2. 7.3.2 SENSE
        1. 7.3.2.1 Adjustable Voltage Thresholds
        2. 7.3.2.2 SENSE Hysteresis
        3. 7.3.2.3 Reverse Polarity Protection
      3. 7.3.3 Output Logic Configurations
        1. 7.3.3.1 Open-Drain
        2. 7.3.3.2 Active-Low (OUT A and OUT B)
        3. 7.3.3.3 Latching
      4. 7.3.4 User-Programmable Release Time Delay
        1. 7.3.4.1 Deassertion Time Delay Configuration
      5. 7.3.5 User-Programmable Sense Delay
        1. 7.3.5.1 Sense Time Delay Configuration
      6. 7.3.6 Analog Out
      7. 7.3.7 Built-in Self-Test
        1. 7.3.7.1 Latching
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design 1: Off-Battery Monitoring
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Dissipation and Device Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Creepage Distance
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.2.1 Adjustable Voltage Thresholds

Figure 7-3 illustrates an example of how to adjust the voltage threshold with external resistor dividers. The resistors can be calculated depending on the desired voltage threshold and device part number. Adjustable voltage threshold variants bypass the internal resistor ladder.

For example, consider a 48V rail, VMON, being monitored for undervoltage (UV) only using of the TPS37100Z91DDYYRQ1 variant, as shown in Figure 7-3. The monitored UV threshold, denoted as VMON-, is the desired voltage where the device asserts the reset. For this example VMON- = 40V. To assert an undervoltage reset the voltage at the sense pin, VSENSE, needs to be equal or lower to the input threshold positive, VITN. For this example variant VSENSE = VITN = 0.8V. Using R1 and R2 the correlation between VMON- and VSENSE can be seen in Equation 1. Assuming R2 = 2kΩ, and R1 can be calculated as R1 = 98kΩ.

Equation 1. VSENSE = VMON- × (R2 ÷ (R1 + R2))

The TPS37100Z91DDYYRQ1 comes with variant specific 1% voltage threshold hysteresis. For the reset signal to become deasserted, VMON must go above VITN + VHYS. For this example variant a 1% voltage threshold hysteresis was selected. Therefore, VMON equals 40.4V when the reset signal becomes deasserted.

TPS37100-Q1 TPS37102-Q1 Adjustable Voltage Threshold with External Resistor DividersFigure 7-3 Adjustable Voltage Threshold with External Resistor Dividers