The TPS3762-Q1 has a Built-In Self-Test (BIST) feature that runs diagnostics internally in the device. During power-up BIST is initiated automatically after crossing V_DD(min). During BIST the BIST pin and RESET output asserts low and deasserts if the BIST test completes successfully indicating no internal faults in the device. The length of the BIST and BIST assertion is specified by t_BIST. If BIST is not successful, the BIST pin will say asserted low signifying an internal fault. The RESET output will stay assert on BIST failure. During BIST, the device is not monitoring the SENSE pin for faults and the RESET is not dependent on the SENSE pin voltage. The BIST sequence of internal tests verifies the internal signal chain of the device by checking for faults on the internal comparators on the SENSE pin, bandgap voltage, and the RESET output. See Figure 10-10 for more details.

Figure 10-10 TPS3762-Q1 Start-Up Sequence

After a successful power-up sequence, BIST can be initiated any time with a logic high input (V_{BIST_EN} or V_{BIST_EN/LATCH_CLR} > 1.3V) on the BIST_EN / LATCH_CLR pin. BIST initiates and the BIST pin asserts only if the SENSE pin is not in a overvoltage or undervoltage fault mode. During this BIST test time period, t_BIST, BIST pin asserts low to signify that BIST has started and RESET assertion is dependent on the device variant. Upon a successful BIST the BIST pin and RESET pin are deasserted. If BIST is not successful due to an internal device not working properly, the RESET pin and BIST pin remain asserted low signifying a fault internal to the device. See Figure 10-11 and Figure 10-12 for more details.

Figure 10-11 BIST With RESET Assertion

Figure 10-12 BIST With No RESET Assertion

Figure 10-13 BIST Fail With RESET Assertion

Figure 10-14 BIST Fail With No RESET Assertion