JAJSRP6A October 2023 – May 2024 TPS3762-Q1
PRODUCTION DATA
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
VDD | 1 | I | Input Supply Voltage: Supply voltage pin. For noisy systems, bypass with a 0.1µF capacitor to GND. |
SENSE | 2 | I | Sense Voltage: Connect this pin to the supply rail that must be monitored. See Section 8.3.2 for more details. Sensing Topology: Overvoltage (OV) or Undervoltage (UV) or Window (OV + UV) |
GND | 3 | - | Ground. Ground pin. All GND pins must be electrically connected to the board ground. |
RESET | 4 | O | Output Reset Signal: RESET asserts when SENSE crosses the voltage threshold after the sense time delay, set by CTS, and remains asserted for the reset time delay period, set by CTR, after SENSE transitions out of a fault condition. For latch variants RESET remains asserted until the latch is cleared. The active low open-drain reset output requires an external pullup resistor. See Section 8.3.3.2 for more details. Output topology: Open-Drain Active-Low |
BIST | 5 | O | Built-In Self-Test: BIST asserts when a logic high input occurs on the BIST_EN / LATCH_CLR or BIST_EN pin, this initiates the internal BIST testing. BIST recovers after tBIST to signify BIST completed successfully. BIST remains asserted for a time period longer than tBIST if there is a failure during BIST. BIST active-low open-drain output requires an external pullup resistor. See Section 8.3.6 for more details. |
BIST_EN / LATCH_CLR | 6 | I | Built-in Self-test Enable and Latch Clear: A logic high input must occur on the BIST_EN / LATCH_CLR to initate BIST and clear a latched OV/UV fault. See Section 8.3.6 for more details. |
CTR | 7 | O | RESET Time Delay: User-programmable reset time delay for RESET. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay. See Section8.3.4 for more details. |
CTS | 8 | O | SENSE Time Delay: User-programmable sense time delay for SENSE. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay. See Section 8.3.5 for more details. |