JAJSRP6A October 2023 – May 2024 TPS3762-Q1
PRODUCTION DATA
For example, consider a 12V rail, VMON, being monitored for overvoltage (OV) using of the TPS3762D02OVDDFRQ1 variant, as shown in Figure 11-1. The monitored OV threshold, denoted as VMON+, is the desired voltage where the device asserts the reset. For this example VMON+ = 35V. To assert an overvoltage reset the voltage at the sense pin, VSENSE, needs to be equal to the input threshold positive, VITP. For this example variant VSENSE = VITP = 0.8V. Using R1 and R2 the correlation between VMON+ and VSENSE can be seen in Equation 8. Assuming R2 = 10kΩ, and R1 can be calculated as R1 = 427.5kΩ.
The TPS3762D02OVDDFRQ1 comes with variant specific 2%, 5%, or 10% voltage threshold hysteresis. For the reset signal to become deasserted, VMON must go below VITP - VHYS. For this example variant a 2% voltage threshold hysteresis was selected. Therefore, VMON equals 34.3V when the reset signal becomes deasserted.
There are inaccuracies that must be taken into consideration while adjusting voltage thresholds. Aside from the tolerance of the resistor divider, there is the internal resistance of the SENSE pin that can affect the accuracy of the resistor divider. Although expected to be very high impedance, users are recommended to calculate the values for the design specifications. The internal SENSE resistance (RSENSE) can be calculated by the SENSE voltage (VSENSE) divided by the SENSE current (ISENSE) as shown in Equation 9. VSENSE can be calculated using Equation 7 depending on the resistor divider and monitored voltage. ISENSE can be calculated using Equation 8.