JAJSRQ5A October   2023  – December 2023 TPS3762

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Specifications
    2. 6.2 Absolute Maximum Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Requirements
    7. 6.7 Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristic
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 7.3.1.2 Power-On Reset (VDD < VPOR )
      2. 7.3.2 SENSE
        1. 7.3.2.1 Reverse Polarity Protection
        2. 7.3.2.2 SENSE Hysteresis
      3. 7.3.3 Output Logic Configurations
        1. 7.3.3.1 Open-Drain
        2. 7.3.3.2 Active-Low (RESET)
        3. 7.3.3.3 Latching
      4. 7.3.4 User-Programmable Reset Time Delay
        1. 7.3.4.1 Reset Time Delay Configuration
      5. 7.3.5 User-Programmable Sense Delay
        1. 7.3.5.1 Sense Time Delay Configuration
      6. 7.3.6 Built-In Self-Test
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Adjustable Voltage Thresholds
    3. 8.3 Typical Application
      1. 8.3.1 Design 1: SELV Power Supply Monitoring
        1. 8.3.1.1 Design Requirements
        2. 8.3.1.2 Detailed Design Procedure
          1. 8.3.1.2.1 Setting Voltage Threshold
          2. 8.3.1.2.2 Meeting the Sense and Reset Delay
          3. 8.3.1.2.3 Setting Supply Voltage
          4. 8.3.1.2.4 Initiating Built-In Self-Test and Clearing Latch
        3. 8.3.1.3 Application Curves
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Dissipation and Device Operation
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-20231212-SS0I-S2C8-2KVS-MCQD7X4BRSGZ-low.svgFigure 5-1 DDF Package,
8-Pin SOT-23,
TPS3762 (Top View)
Table 5-1 Pin Functions

PIN

I/ODESCRIPTION
NAMENO.
VDD1IInput Supply Voltage: Supply voltage pin. For noisy systems, bypass with a 0.1 µF capacitor to GND.
SENSE2I

Sense Voltage: Connect this pin to the supply rail that must be monitored. See SENSE for more details.

Sensing Topology: Overvoltage (OV), Undervoltage (UV), or Window (OV + UV)

GND

3

-Ground. Ground pin. All GND pins must be electrically connected to the board ground.
RESET4O

Output Reset Signal: RESET asserts when SENSE crosses the voltage threshold after the sense time delay, set by CTS and remains asserted for the reset time delay period after SENSE transitions out of a fault condition. For latch variants RESET remains asserted until the latch is cleared. The active low open-drain reset output requires an external pullup resistor. See Section 7.3.3 for more details.

Output topology: Open-Drain Active-Low

BIST5

O

Built-In Self-Test: BIST asserts when a logic high input occurs on the BIST_EN / LATCH_CLR or BIST_EN pin, this initiates the internal BIST testing. BIST recovers after tBIST to signify BIST completed successfully. BIST will remain asserted for a time period longer than tBIST if there is a failure during BIST. BIST active-low open-drain output requires an external pullup resistor. See Section 7.3.6 for more details.

BIST_EN / LATCH_CLR

6

I

Built-In Self-Test Enable and Latch Clear: A logic high input must occur on the BIST_EN / LATCH_CLR to initate BIST and clear a latched OV/UV fault. See Section 7.3.6 and Section 7.3.3.3 for more details.
CTR7

O

RESET Time Delay: User-programmable reset time delay for RESET. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay. See Section 7.3.4 for more details.

CTS

8

O

SENSE Time Delay: User-programmable sense time delay for SENSE. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay. See Section 7.3.5 for more details.