JAJSK33A April   2022  – September 2023 TPS38

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1.     8
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 8.3.1.2 Power-On Reset (VDD < VPOR )
      2. 8.3.2 SENSE
        1. 8.3.2.1 SENSE Hysteresis
      3. 8.3.3 Output Logic Configurations
        1. 8.3.3.1 Open-Drain
        2. 8.3.3.2 Push-Pull
        3. 8.3.3.3 Active-High (RESET)
        4. 8.3.3.4 Active-Low (RESET)
      4. 8.3.4 User-Programmable Reset Time Delay
        1. 8.3.4.1 Reset Time Delay Configuration
      5. 8.3.5 User-Programmable Sense Delay
        1. 8.3.5.1 Sense Time Delay Configuration
      6. 8.3.6 Manual RESET (CTR1 / MR) and (CTR2 / MR) Input
      7. 8.3.7 Adjustable Voltage Thresholds
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 High Voltage – Fast AC Signal Monitoring For Power Fault Detection
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Dissipation and Device Operation
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Creepage Distance
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-20210804-CA0I-QSDD-WX8N-Q5NFV26X45MZ-low.svg Figure 6-1 DSK Package,
10-Pin WSON,
TPS38 (Top View)









GUID-20210831-SS0I-PQPW-HBLJ-2SJK3SP8FTCV-low.svg Figure 6-2 DYY Package,
14-Pin SOT-23,
TPS38 (Top View)
Table 6-1 Pin Functions
PIN NAME WSON (DSK) SOT23 (DYY) I/O DESCRIPTION
PIN NUM. PIN NUM.
VDD 1 1 I Input Supply Voltage: Bypass with a 0.1 µF capacitor to GND.
SENSE1 2 3 I

This pin is connected to the voltage that will be monitored for fixed variants or to a resistor divider for the adjustable variant. Depending on the SENSE1 sensing configuration, when the voltage on SENSE1 pin detects an undervoltage (UV) or an overvoltage (OV) fault, RESET1/RESET1 asserts after the sense time delay, set by CTS1. When the voltage on the SENSE1 pin transitions back to an unfaulty UV or OV state, RESET1/RESET1 deasserts after the reset time delay, set by CTR1. For noisy applications, placing a 10 nF to 100 nF ceramic capacitor close to this pin may be needed for optimum performance.
SENSE2 3 4 I

This pin is connected to the voltage that will be monitored for fixed variants or to a resistor divider for the adjustable variant. Depending on the SENSE2 sensing configuration, when the voltage on SENSE2 pin detects an undervoltage (UV) or an overvoltage (OV) fault, RESET2/RESET2 asserts after the sense time delay, set by CTS2. When the voltage on the SENSE2 pin transitions back to an unfaulty UV or OV state, RESET2/RESET2 deasserts after the reset time delay, set by CTR2. For noisy applications, placing a 10 nF to 100 nF ceramic capacitor close to this pin may be needed for optimum performance.
RESET1/RESET1 4 6 O

Output Reset Signal For Channel 1: See Section 5 for output topology options. RESET1/RESET1 asserts when SENSE1 detects an undervoltage or overvoltage fault condition. RESET1/RESET1 remains asserted for the reset time delay period after SENSE1 transitions out of an UV or OV fault condition. For active low open-drain reset output, an external pullup resistor is required. Do not place external pullup resistors on push-pull outputs.

Reset output signal for: SENSE1

Sensing Topology: Undervoltage (UV) or Overvoltage (OV)

Output topology: Open Drain or Push Pull, Active Low or Active High
RESET2/RESET2 5 7 O

Output Reset Signal For Channel 2: See Section 5 for output topology options. RESET2/RESET2 asserts when SENSE2 detects an undervoltage or overvoltage fault condition. RESET2/RESET2 remains asserted for the reset time delay period after SENSE2 transitions out of an UV or OV fault condition. For active low open-drain reset output, an external pullup resistor is required.

Reset output signal for: SENSE2

Sensing Topology: Undervoltage (UV) or Overvoltage (OV)

Output topology: Open Drain, Active Low or Active High
CTR1/ MR 6 9 -

Channel 1 RESET Time Delay: User-programmable reset time delay for RESET1/RESET1. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay.

Manual Reset: If this pin is driven low, the RESET1/RESET1 output will reset and become asserted. The pin can be left floating or be connected to a capacitor. This pin should not be driven high.
CTR2/ MR 9 12 - Channel 2 RESET Time Delay: User-programmable reset time delay for RESET2/RESET2. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay.

Manual Reset: If this pin is driven low, the RESET2/RESET2 output will reset and become asserted. The pin can be left floating or be connected to a capacitor. This pin should not be driven high.
GND 10 8, 13 - Ground. All GND pins must be electrically connected to the board ground.
NC PAD 2, 5, 14 -

The PAD for the DSK package is not internally connected, the PAD can be connected to GND or be left floating. For the DYY package, NC stands for “No Connect”. The pins are to be left floating.
CTS1 7 10 O Channel 1 SENSE Time Delay: Capacitor programmable sense delay: CTS1 pin offers a user-adjustable sense delay time when asserting a reset condition. Connecting this pin to a ground-referenced capacitor sets the RESET1/RESET1 delay time to assert.
CTS2 8 11 O Channel 2 SENSE Time Delay: Capacitor programmable sense delay: CTS2 pin offers a user-adjustable sense delay time when asserting a reset condition. Connecting this pin to a ground-referenced capacitor sets the RESET2/RESET2 delay time to assert.