SLVS292F June   2000  – September 2019 TPS3836 , TPS3837 , TPS3838

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Dissipation Ratings
    3. 7.3 ESD Ratings
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagram
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input Voltage (VDD)
      2. 9.3.2 Manual Reset (MR)
      3. 9.3.3 Selectable Reset Delay (CT)
      4. 9.3.4 Reset Output (RESET / RESET)
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DBV|5
サーマルパッド・メカニカル・データ
発注情報

10.2.3 Application Curves

This section shows the voltage monitoring functionality. Figure 9 shows when VDD drops below 2.93 V, the RESET output asserts to active low. Figure 10 shows that when the VDD rises above 2.93 V + 40 mV = approximately 2.97 V for 200 ms, the RESET output deasserts to inactive logic high.

TPS3836 TPS3837 TPS3838 VDD_falling_prop_delay_TPS3836K33.gifFigure 9. VDD Falling Below VIT Triggers a RESET Assertion After tPHL
TPS3836 TPS3837 TPS3838 VDD_rising_reset_delay_TPS3836K33.gifFigure 10. VDD Rising Above VIT + VHYS for tD Releases RESET to Inactive