SLVS292F June   2000  – September 2019 TPS3836 , TPS3837 , TPS3838

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Dissipation Ratings
    3. 7.3 ESD Ratings
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagram
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input Voltage (VDD)
      2. 9.3.2 Manual Reset (MR)
      3. 9.3.3 Selectable Reset Delay (CT)
      4. 9.3.4 Reset Output (RESET / RESET)
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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発注情報

7.6 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage RESET (TPS3836) VDD = 3.3 V, IOH = –2 mA 0.8 × VDD V
VDD = 6 V, IOH = –3 mA
RESET (TPS3837) VDD = 1.8 V, IOH = –1 mA
VDD = 3.3 V, IOL = –2 mA
VOL Low-level output voltage RESET (TPS3836, TPS3838) VDD = 1.8 V, IOL = 1 mA 0.4 V
VDD = 3.3 V, IOL = 2 mA
RESET (TPS3837) VDD = 3.3 V, IOL = 2 mA
VDD = 6 V, IOL = 3 mA
Power-up reset voltage(1) TPS3836, TPS3838 VDD  ≥ 1.1 V, IOL = 50 μA 0.2 V
TPS3837 VDD  ≥ 1.1 V, IOL = –50 μA 0.8 × VDD V
VIT Negative-going input threshold voltage(2) TPS383xE18 TA = –40°C to 85°C 1.66 1.71 1.74 V
TPS383xJ25 2.18 2.25 2.29
TPS383xH30 2.70 2.79 2.85
TPS383xL30 2.56 2.64 2.69
TPS383xK33 2.84 2.93 2.99
VHYS Hysteresis at VDD input 1.7 V < VIT < 2.5 V 30 mV
2.5 V < VIT < 3.5 V 40
3.5 V < VIT < 5 V 50
IIH High-level input current MR(3) MR = 0.7 × VDD, VDD = 6 V –40 –60 –100 μA
CT CT = VDD = 6 V –25 25 nA
IIL Low-level input current MR(3) MR = 0 V, VDD = 6 V –130 –200 –340 μA
CT CT = 0 V, VDD = 6 V –25 25 nA
IOH High-level output current TPS3838 VDD = VIT + 0.2 V, VOH = VDD 25 nA
IDD Supply current VDD > VIT, VDD < 3 V 220 400 nA
VDD > VIT, VDD > 3 V 250 450
VDD < VIT 10 15 μA
Internal pullup resistor at MR 30 kΩ
CI Input capacitance at MR and CT VI = 0 V to VDD 5 pF
(1) The lowest voltage at which the RESET output becomes active. tR, VDD ≥ 15 μs/V.
(2) To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 μF) should be placed near the supply terminal.
(3) If manual reset is unused, MR should be connected to VDD to minimize current consumption.