JAJSGL5C December   2018  – August 2019 TPS3840

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
      2.      TPS3840 の標準的な消費電流
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input Voltage (VDD)
        1. 9.3.1.1 VDD Hysteresis
        2. 9.3.1.2 VDD Transient Immunity
      2. 9.3.2 User-Programmable Reset Time Delay
      3. 9.3.3 Manual Reset (MR) Input
      4. 9.3.4 Output Logic
        1. 9.3.4.1 RESET Output, Active-Low
        2. 9.3.4.2 RESET Output, Active-High
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Operation (VDD > VDD(min))
      2. 9.4.2 VDD Between VPOR and VDD(min)
      3. 9.4.3 Below Power-On-Reset (VDD < VPOR)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Design 2: Battery Voltage and Temperature Monitor
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
      3. 10.2.3 Design 3: Fast Start Undervoltage Supervisor with Level-shifted Input
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
      4. 10.2.4 Design 4: Voltage Monitor with Back-up Battery Switchover
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedure
      5. 10.2.5 Application Curve: TPS3840EVM
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイスの項目表記
    2. 13.2 コミュニティ・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

DBV Package
5-Pin SOT-23
TPS3840PL, TPS3840DL Top View
TPS3840 pinout-TPS3840PL-DBV-pkg-SNVSB03.gifFigure 1. Pin Configuration TPS3840PL, TPS3840DL
DBV Package
5-Pin SOT-23
TPS3840PH Top View
TPS3840 pinout-TPS3840PH-DBV-pkg-SNVSB03.gifFigure 2. Pin Configuration TPS3840PH

Pin Functions

PIN I/O DESCRIPTION
NAME TPS3840PL, TPS3840DL TPS3840PH
RESET N/A 1 O Active-High Output Reset Signal: This pin is driven high when either the MR pin is driven to a logic low or VDD voltage falls below the negative voltage threshold (VIT-). RESET remains high (asserted) for the delay time period (tD) after both MR is floating or above VMR_L and VDD voltage rise above VIT+.
RESET 1 N/A O Active-Low Output Reset Signal: This pin is driven logic when either the MR pin is driven to a logic low or VDD voltage falls below the negative voltage threshold (VIT-). RESET remains low (asserted) for the delay time period (tD) after both MR is floating or above VMR_L and VDD voltage rise above VIT+.
VDD 2 2 I Input Supply Voltage. TPS3840 monitors VDD voltage
GND 3 3 _ Ground
MR / NC 4 4 I Manual Reset. Pull this pin to a logic low (VMR_L) to assert a reset signal in the output pin. After the MR pin is left floating or pull to VMR_H the output goes to the nominal state after the reset delay time(tD) expires. MR can be left floating when not in use. NC stands for "No Connection" or floating.
CT 5 5 - Capacitor Time Delay Pin. The CT pin offers a user-programmable delay time. Connect an external capacitor on this pin to adjust time delay. When not in use leave pin floating for the smallest fixed time delay.