JAJSD46B January 2017 – September 2021 TPS3850-Q1
PRODUCTION DATA
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The watchdog is often needed to be disabled during startup to allow for an initialization period. When the initialization period is over, the watchdog timer is turned back on to allow the microcontroller to be monitored by the TPS3850-Q1. To achieve this setup, SET0 must start at VDD and SET1 must start at GND. In this design, SET0 is simply tied to VDD and SET1 is controlled by a TPS3890-Q1 supervisor. In this application, the TPS3890-Q1 was chosen to monitor VDD as well, which means that RESET on the TPS3890-Q1 stays low until VDD rises above VITN. When VDD comes up, the delay time can be adjusted through the CT capacitor on the TPS3890-Q1. With this approach, the RESET delay can be adjusted from a minimum of 25 µs to a maximum of 30 seconds. For this design, a minimum delay of 7 seconds is needed until the watchdog timer is enabled. The CT capacitor calculation (see the TPS3890-Q1 data sheet) yields an ideal capacitance of 6.59 µF, giving a closest standard ceramic capacitor value of 6.8 µF. When connecting a 6.8-µF capacitor from CT to GND, the typical delay time is 7.21 seconds. Figure 8-13 illustrates the typical startup waveform for this circuit when the watchdog input is off. Figure 8-13 illustrates that when the watchdog is disabled, the WDO output remains high. See the TPS3890-Q1 data sheet for detailed information on the TPS3890-Q1.