JAJSD46B January   2017  – September 2021 TPS3850-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 CRST
      2. 7.3.2 RESET
      3. 7.3.3 Over- and Undervoltage Fault Detection
      4. 7.3.4 Adjustable Operation Using the TPS3850H01Q1
      5. 7.3.5 Window Watchdog
        1. 7.3.5.1 SET0 and SET1
          1. 7.3.5.1.1 Enabling the Window Watchdog
          2. 7.3.5.1.2 Disabling the Watchdog Timer When Using the CRST Capacitor
          3. 7.3.5.1.3 SET0 and SET1 During Normal Watchdog Operation
      6. 7.3.6 Window Watchdog Timer
        1. 7.3.6.1 CWD
        2. 7.3.6.2 WDI Functionality
        3. 7.3.6.3 WDO Functionality
    4. 7.4 Device Functional Modes
      1. 7.4.1 VDD is Below VPOR ( VDD < VPOR)
      2. 7.4.2 Above Power-On-Reset But Less Than UVLO (VPOR ≤ VDD < VUVLO)
      3. 7.4.3 Above UVLO But Less Than VDD (min) (VUVLO ≤ VDD < VDD (min))
      4. 7.4.4 Normal Operation (VDD ≥ VDD (min))
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 CRST Delay
        1. 8.1.1.1 Factory-Programmed Reset Delay Timing
        2. 8.1.1.2 Programmable Reset Delay Timing
      2. 8.1.2 CWD Functionality
        1. 8.1.2.1 Factory-Programmed Timing Options
        2. 8.1.2.2 Adjustable Capacitor Timing
        3. 8.1.2.3 45
      3. 8.1.3 Adjustable SENSE Configuration
      4. 8.1.4 Overdrive on the SENSE Pin
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Monitoring a 1.2-V Rail with Factory-Programmable Watchdog Timing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Monitoring the 1.2-V Rail
          2. 8.2.1.2.2 Meeting the Minimum Reset Delay
          3. 8.2.1.2.3 Setting the Watchdog Window
          4. 8.2.1.2.4 Calculating the RESET and WDO Pullup Resistor
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2: Using the TPS3850H01Q1 to Monitor a 0.7-V Rail With an Adjustable Window Watchdog Timing
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Meeting the Minimum Reset Delay
          2. 8.2.2.2.2 Setting the Window Watchdog
          3. 8.2.2.2.3 Watchdog Disabled During the Initialization Period
          4. 8.2.2.2.4 Calculating the Sense Resistor
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Module
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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発注情報

6.5 Electrical Characteristics

at 1.6 V ≤ VDD ≤ 6.5 V over the operating temperature range of –40°C ≤ TA, TJ ≤ +125°C (unless otherwise noted); the open-drain pullup resistors are 10 kΩ for each output; typical values are at TJ = 25°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
GENERAL CHARACTERISTICS
VDD(1)(2)(3)Supply voltage1.66.5V
IDDSupply current 1019µA
RESET FUNCTION
VPOR(2)Power-on-reset voltageIRESET = 15 µA, VOL(MAX) = 0.25 V 0.8V
VUVLO(1)Undervoltage lockout voltage1.35V
VIT+(OV)Overvoltage SENSE threshold accuracy, entering RESETVIT+(nom)–0.8%VIT+(nom)+0.8%
VIT-(UV)Undervoltage SENSE threshold accuracy, entering RESETVIT-(nom)–0.8%VIT-(nom)+0.8%
VIT(ADJ)Falling SENSE threshold voltage, adjustable version only0.39680.40.4032V
VHYSTHysteresis voltage0.2%0.5%0.8%
ICRSTCRST pin charge currentCRST = 0.5 V 337375413nA
VCRSTCRST pin threshold voltage1.1921.211.228V
WINDOW WATCHDOG FUNCTION
ICWDCWD pin charge currentCWD = 0.5 V 347 375403nA
VCWDCWD pin threshold voltage1.1961.211.224V
VOLRESET, WDO output lowVDD = 5 V, ISINK = 3 mA0.4V
IDRESET, WDO output leakage currentVDD = 1.6 V, VRESET, = VWDO = 6.5 V1µA
VILLow-level input voltage (SET0, SET1)0.25V
VIHHigh-level input voltage (SET0, SET1)0.8V
VIL(WDI)Low-level input voltage (WDI)0.3 × VDDV
VIH(WDI)High-level input voltage (WDI)0.8 × VDDV
ISENSESENSE pin idle currentTPS3850Xyy(y), VSENSE = 5.0 V,
VDD = 3.3 V		2.12.5µA
TPS3850H01 only, VSENSE = 5.0 V, VDD = 3.3 V–5050nA
(1) When VDD falls below VUVLO, RESET is driven low.
(2) When VDD falls below VPOR, RESET and WDO are undefined.
(3) During power-on, VDD must be a minimum 1.6 V for at least 300 µs before the output corresponds to the SENSE voltage.