JAJSD46B January 2017 – September 2021 TPS3850-Q1
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
PARAMETER | DESIGN REQUIREMENT | DESIGN RESULT |
---|---|---|
Reset delay | Minimum RESET delay of 150 ms | Minimum RESET delay of 170 ms |
Watchdog disable for initialization period | Watchdog must remain disabled for 7 seconds until logic enables the watchdog timer | 7.21 seconds (typ) |
Watchdog window | 250 ms, maximum | tWDL(max) = 135 ms, tWDU(min) = 181 ms |
Output logic voltage | 3.3-V CMOS | 3.3-V CMOS |
Monitored rail | 0.7 V, with 7% threshold | VITN (max) 0.667 V (–4.7%) |
VITN (typ) 0.65 V (–6.6%) | ||
VITN (min) 0.641 V (–8.5%) | ||
Maximum device current consumption | 50 µA | 10 µA of current consumption typical, worst-case of 52 μA when WDO or RESET is asserted(1) |