JAJSD46B January 2017 – September 2021 TPS3850-Q1
PRODUCTION DATA
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When VDD is less than VUVLO, and greater than or equal to VPOR, the RESET signal is asserted (logic low) regardless of the voltage on the SENSE pin. When RESET is asserted, the watchdog output WDO is in a high-impedance state regardless of the WDI signal that is input to the device.