JAJSCT6B October   2016  – September 2021 TPS3850

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 CRST
      2. 7.3.2 RESET
      3. 7.3.3 Over- and Undervoltage Fault Detection
      4. 7.3.4 Adjustable Operation Using the TPS3850H01
      5. 7.3.5 Window Watchdog
        1. 7.3.5.1 SET0 and SET1
          1. 7.3.5.1.1 Enabling the Window Watchdog
          2. 7.3.5.1.2 Disabling the Watchdog Timer When Using the CRST Capacitor
          3. 7.3.5.1.3 SET0 and SET1 During Normal Watchdog Operation
      6. 7.3.6 Window Watchdog Timer
        1. 7.3.6.1 CWD
        2. 7.3.6.2 WDI Functionality
        3. 7.3.6.3 WDO Functionality
    4. 7.4 Device Functional Modes
      1. 7.4.1 VDD is Below VPOR ( VDD < VPOR)
      2. 7.4.2 Above Power-On-Reset But Less Than UVLO (VPOR ≤ VDD < VUVLO)
      3. 7.4.3 Above UVLO But Less Than VDD (min) (VUVLO ≤ VDD < VDD (min))
      4. 7.4.4 Normal Operation (VDD ≥ VDD (min))
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 CRST Delay
        1. 8.1.1.1 Factory-Programmed Reset Delay Timing
        2. 8.1.1.2 Programmable Reset Delay-Timing
      2. 8.1.2 CWD Functionality
        1. 8.1.2.1 Factory-Programmed Timing Options
        2. 8.1.2.2 Adjustable Capacitor Timing
      3. 8.1.3 Adjustable SENSE Configuration
      4. 8.1.4 Overdrive on the SENSE Pin
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Monitoring a 1.2-V Rail with Factory-Programmable Watchdog Timing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Monitoring the 1.2-V Rail
          2. 8.2.1.2.2 Meeting the Minimum Reset Delay
          3. 8.2.1.2.3 Setting the Watchdog Window
          4. 8.2.1.2.4 Calculating the RESET and WDO Pullup Resistor
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2: Using TPS3850H01 to monitor a 0.7-V Rail With an Adjustable Window Watchdog Timing
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Meeting the Minimum Reset Delay
          2. 8.2.2.2.2 Setting the Window Watchdog
          3. 8.2.2.2.3 Watchdog Disabled During the Initialization Period
          4. 8.2.2.2.4 Calculating the Sense Resistor
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Revision History

Changes from Revision A (November 2016) to Revision B (September 2021)

  • 文書全体にわたって表、図、相互参照の採番方法を更新Go
  • 「±15% 精度の WDT および RST 遅延」を削除Go
  • Web サイトへのリンクを含むようにアプリケーションを更新Go
  • 「SENSE ピンの」を追加Go
  • Changed VESD values to ±4000 V and ±1000 VGo
  • Changed ICWD min and max spec Go
  • Changed VCWD min and max spec Go
  • Added a footnote to for tINIT Go
  • Changed minimum and maximum specifications of 2nd, 5th, 6th, and 8th rows of tWDL parameter Go
  • Changed minimum and maximum specifications of 2nd and last rows of tWDU parameter Go
  • Added new section "Disabling the Watchdog Timer When Using the CRST Capacitor"Go
  • Changed 0.000381 to 0.000324 and 0.000438 in Equation 4 and Equation 5, respectivelyGo
  • Changed minimum and maximum specifications in 100 pF and 1 nF rows of Reset Delay Time for Common Ideal Capacitor Values tableGo
  • Changed minimum and maximum specifications for NC SETx 01 setting for both upper and lower watchdog boundaries, 10 kΩ to VDD SETx 00 and 01 settings for lower watchdog boundary, and 10 kΩ to VDD SETx 11 setting for both upper and lower watchdog boundaries in Factory-Programmed Watchdog Timing tableGo
  • Changed minimum and maximum limits on tWDU and added explanation. Go
  • Changed 0.000381 to 0.000324 in Equation 11Go
  • Changed description of factory-programmed timing options and values of tWDL(max) and tWDU(min) in Setting the Watchdog Window sectionGo
  • Changed 0.85 to 0.905 in Equation 14Go
  • Changed Equation 17 and Equation 18 so that ISENSE is no longer in the denominatorGo

Changes from Revision * (October 2016) to Revision A (November 2016)

  • Changed units in ISENSE parameter and footnote 1 in Electrical Characteristics table Go
  • Added correct operation state to Figure 2 Go
  • Changed Figure 3 so the SET pins do not bring the watchdog into the disabled state before going to the 1:2 ratioGo
  • Changed Figure 11 so it no longer has VDD and VSENSE tied together Go
  • Changed Figure 26 so it no longer goes through watchdog disabledGo
  • Added correct operation state to Figure 27 Go
  • Changed RESET to WDO in description of WDO assertion in WDO Functionality section Go