JAJSCO1A November   2016  – September 2021 TPS3851

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 RESET
      2. 7.3.2 Manual Reset MR
      3. 7.3.3 UV Fault Detection
      4. 7.3.4 Watchdog Mode
        1. 7.3.4.1 CWD
        2. 7.3.4.2 Watchdog Input WDI
        3. 7.3.4.3 Watchdog Output WDO
        4. 7.3.4.4 SET1
    4. 7.4 Device Functional Modes
      1. 7.4.1 VDD is Below VPOR ( VDD < VPOR)
      2. 7.4.2 Above Power-On-Reset, But Less Than VDD(min) (VPOR ≤ VDD < VDD(min))
      3. 7.4.3 Normal Operation (VDD ≥ VDD(min))
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 CWD Functionality
        1. 8.1.1.1 Factory-Programmed Timing Options
        2. 8.1.1.2 Adjustable Capacitor Timing
      2. 8.1.2 Overdrive Voltage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Monitoring the 1.8-V Rail
        2. 8.2.2.2 Calculating RESET and WDO Pullup Resistor
        3. 8.2.2.3 Setting the Watchdog
        4. 8.2.2.4 Watchdog Disabled During Initialization Period
      3. 8.2.3 Glitch Immunity
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Timing Requirements

at VITN + VHYST ≤ VDD ≤ 6.5 V over the operating temperature range of –40°C ≤ TA, T A ≤ 125°C (unless otherwise noted); the open-drain pullup resistors are 10 kΩ for each output; typical values are at TA = 25°C
MINNOMMAXUNIT
GENERAL
tINITCWD pin evaluation period (1)381µs
Minimum MR, SET1 pin pulse duration1µs
Startup delay (2)300µs
RESET FUNCTION
tRSTReset timeout period170200230ms
tRST-DELVDD to RESET delayVDD = VITN + VHYST + 2.5%35µs
VDD = VITN – 2.5%17
tMR-DELMR to RESET delay200ns
WATCHDOG FUNCTION
tWDWatchdog timeout (3)CWD = NC, SET1 = 0 (4)Watchdog disabled
CWD = NC, SET1 = 1 (4)136016001840ms
CWD = 10 kΩ to VDD,
SET1 = 0 (4)		Watchdog disabled
CWD = 10 kΩ to VDD,
SET1 = 1 (4)		170200230ms
tWD-setupSetup time required for device to respond to changes on WDI after being enabled150µs
Minimum WDI pulse duration50ns
tWD-delWDI to WDO delay50ns
(1) Refer to Section 8.1.1.2
(2) During power-on, VDD must be a minimum 1.6 V for at least 300 µs before RESET correlates with VDD
(3) The fixed watchdog timing covers both standard and extended versions.
(4) SET1 = 0 means VSET1 < VIL; SET1 = 1 means VSET1 > VIH.