JAJSQG3B march   2022  – may 2023 TPS389006-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I2C
      2. 8.3.2 Auto Mask (AMSK)
      3. 8.3.3 PEC
      4. 8.3.4 VDD
      5. 8.3.5 MON
      6. 8.3.6 NIRQ
      7. 8.3.7 ADC
      8. 8.3.8 Time Stamp
    4. 8.4 Device Functional Modes
      1. 8.4.1 Built-In Self Test and Configuration Load
        1. 8.4.1.1 Notes on BIST Execution
      2. 8.4.2 TPS389006-Q1 Power ON
      3. 8.4.3 General Monitoring
        1. 8.4.3.1 IDLE Monitoring
        2. 8.4.3.2 ACTIVE Monitoring
        3. 8.4.3.3 Sequence Monitoring 1
          1. 8.4.3.3.1 ACT Transitions 0→1
          2. 8.4.3.3.2 SLEEP Transition 1→0
          3. 8.4.3.3.3 SLEEP Transition 0→1
        4. 8.4.3.4 Sequence Monitoring 2
          1. 8.4.3.4.1 ACT Transition 1→0
    5. 8.5 Register Maps
      1. 8.5.1 BANK0 Registers
      2. 8.5.2 BANK1 Registers
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

I2C

The TPS389006-Q1 device follows the I2C protocol (up to 1MHz) to manage communication with host devices such as a MCU or System on Chip (SoC). I2C is a two wire communication protocol implmented using two signals, clock (SCL) and data (SDA). The host device is the primary controller of communication. TPS389006-Q1 device responds over the data line during read or write operations as defined by I2C protocol. Both SCL and SDA signals are open drain topology and can be used in a wired-OR configuration with other devices to share the communication bus. Both SCL and SDA pins need an external pull up resistor to supply voltage (10 kΩ recommended).

Figure 8-2 shows the timing relationship between SCL and SDA lines to transfer 1 byte of data. SCL line is always controlled by host. To transfer 1 byte data, host needs to send 9 clocks on SCL. 8 clocks for data and 1 clock for ACK or NACK. SDA line is controlled by either the host or TPS389006-Q1 device based on the read or write operation. Figure 8-2 and Figure 8-3 highlight the communication protocol flow and which device controls SDA line at various instances during active communication.

GUID-20230413-SS0I-ZDNW-G9RJ-WDWHBSC0RJ3M-low.svg Figure 8-2 SCL to SDA Timing for 1 Byte Data Transfer
GUID-20230531-SS0I-G0ZL-GVTN-RHGRLFFVJG4B-low.svg Figure 8-3 I2C Write Protocol
GUID-20230531-SS0I-CCMH-JRZL-3ZZKK0FPWJHF-low.svg Figure 8-4 I2C Read Protocol

Before initiating communication over I2C protocol, host needs to confirm the I2C bus is available for communication. Monitor the SCL and SDA lines, if any line is pulled low, the I2C bus is occupied. Host needs to wait until the bus is available for communication. Once the bus is available for communication, the host can initiate read or write operation by issuing a START condition. Once the I2C communication is complete, release the bus by issuing STOP command. Figure 8-5 shows how to implement START and STOP condition.

GUID-20230413-SS0I-STGZ-DVZN-KNPLXXNN30CZ-low.svg Figure 8-5 I2C START and STOP Condition
Table 8-1 shows the different functionality available when programming with I2C.
Table 8-1 User Programmable I2C Functions
FUNCTIONS DESCRIPTION
Thresholds for OV/UV- fast loop Adjustable in 5 mV steps from 0.2 V to 1.475 V and 20 mV steps from 0.8 V to 5.5 V
Thresholds for drift -positive and negative Adjustable in 5 mV steps from 0.2 V to 1.475 V and 20 mV steps from 0.8 V to 5.5 V
Voltage Monitoring scaling 1 or 4
Glitch (debounce) immunity for OV/UV-fast loop 0.1 us to 102.4 us
Enable sequence timeout 1 ms to 4 s
Sleep sequence timeout 1 ms to 4 s
SYNC pulse width 50 us to 2600 us
Expected ON/OFF Sequence on ACT Used for sequence logging
Expected ON/OFF Sequence on Sleep Used for sequence logging
Auto Mask OFF-ON-OFF via ACT Selectable for each MON channel
Auto Mask OFF-ON-OFF via SLEEP Selectable for each MON channel
Packet error checking for I2C Enabling or Disabling
Force NIRQ assertion Controlled by I2C register
Individual channel MON Enable or Disable
Interrupt disable functions BIST, PEC, TSD, CRC