The TPS389006-Q1 device follows the I²C protocol (up to 1MHz) to manage communication with host devices such as a MCU or System on Chip (SoC). I²C is a two wire communication protocol implmented using two signals, clock (SCL) and data (SDA). The host device is the primary controller of communication. TPS389006-Q1 device responds over the data line during read or write operations as defined by I²C protocol. Both SCL and SDA signals are open drain topology and can be used in a wired-OR configuration with other devices to share the communication bus. Both SCL and SDA pins need an external pull up resistor to supply voltage (10 kΩ recommended).

Figure 8-2 shows the timing relationship between SCL and SDA lines to transfer 1 byte of data. SCL line is always controlled by host. To transfer 1 byte data, host needs to send 9 clocks on SCL. 8 clocks for data and 1 clock for ACK or NACK. SDA line is controlled by either the host or TPS389006-Q1 device based on the read or write operation. Figure 8-2 and Figure 8-3 highlight the communication protocol flow and which device controls SDA line at various instances during active communication.

Figure 8-2 SCL to SDA Timing for 1 Byte Data Transfer

Figure 8-3 I²C Write Protocol

Figure 8-4 I²C Read Protocol

Before initiating communication over I²C protocol, host needs to confirm the I²C bus is available for communication. Monitor the SCL and SDA lines, if any line is pulled low, the I²C bus is occupied. Host needs to wait until the bus is available for communication. Once the bus is available for communication, the host can initiate read or write operation by issuing a START condition. Once the I²C communication is complete, release the bus by issuing STOP command. Figure 8-5 shows how to implement START and STOP condition.

Figure 8-5 I²C START and STOP Condition