JAJSQG3B march   2022  – may 2023 TPS389006-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I2C
      2. 8.3.2 Auto Mask (AMSK)
      3. 8.3.3 PEC
      4. 8.3.4 VDD
      5. 8.3.5 MON
      6. 8.3.6 NIRQ
      7. 8.3.7 ADC
      8. 8.3.8 Time Stamp
    4. 8.4 Device Functional Modes
      1. 8.4.1 Built-In Self Test and Configuration Load
        1. 8.4.1.1 Notes on BIST Execution
      2. 8.4.2 TPS389006-Q1 Power ON
      3. 8.4.3 General Monitoring
        1. 8.4.3.1 IDLE Monitoring
        2. 8.4.3.2 ACTIVE Monitoring
        3. 8.4.3.3 Sequence Monitoring 1
          1. 8.4.3.3.1 ACT Transitions 0→1
          2. 8.4.3.3.2 SLEEP Transition 1→0
          3. 8.4.3.3.3 SLEEP Transition 0→1
        4. 8.4.3.4 Sequence Monitoring 2
          1. 8.4.3.4.1 ACT Transition 1→0
    5. 8.5 Register Maps
      1. 8.5.1 BANK0 Registers
      2. 8.5.2 BANK1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2 Design Requirements

Six different voltage rails supplied by DC/DC converters need to be properly monitored in this design. All detected failures in sequencing should be reported via an external hardware interrupt signal. All detected failures should be logged in internal registers and be accessible to an external processor via I2C.