SNVSBM4D March   2022  – October 2024 TPS389006-Q1 , TPS389R0-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I2C
      2. 7.3.2  Auto Mask (AMSK)
      3. 7.3.3  Packet Error Checking (PEC)
      4. 7.3.4  VDD
      5. 7.3.5  MON
      6. 7.3.6  NIRQ
      7. 7.3.7  ADC
      8. 7.3.8  Time Stamp
      9. 7.3.9  NRST
      10. 7.3.10 Register Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS389006/08-Q1,TPS389R0-Q1 Power ON
      3. 7.4.3 General Monitoring
        1. 7.4.3.1 IDLE Monitoring
        2. 7.4.3.2 ACTIVE Monitoring
        3. 7.4.3.3 Sequence Monitoring 1
          1. 7.4.3.3.1 ACT Transitions 0→1
          2. 7.4.3.3.2 SLEEP Transition 1→0
          3. 7.4.3.3.3 SLEEP Transition 0→1
        4. 7.4.3.4 Sequence Monitoring 2
          1. 7.4.3.4.1 ACT Transition 1→0
    5. 7.5 Register Maps
      1. 7.5.1 BANK0 Registers
      2. 7.5.2 BANK1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Multichannel Sequencer and Monitor
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

TPS389006-Q1 TPS389R0-Q1 RTE Package 16-Pin WQFN TPS389006-Q1 Top View Figure 5-1 RTE Package
16-Pin WQFN
TPS389006-Q1 Top View
TPS389006-Q1 TPS389R0-Q1 RTE Package 16-Pin WQFN TPS389R0-Q1 Top View Figure 5-2 RTE Package
16-Pin WQFN
TPS389R0-Q1 Top View
TPS389006-Q1 TPS389R0-Q1 RTE Package 16-Pin WQFN TPS389008-Q1 Top View Figure 5-3 RTE Package
16-Pin WQFN
TPS389008-Q1 Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NO. TPS389006/08-Q1 TPS389R0-Q1
NAME NAME
1 MON3 MON3 I Voltage monitor channel 3
2 MON6 MON6 I Voltage monitor channel 6
3 MON4 MON4 I Voltage monitor channel 4
4 MON5 MON5 I Voltage monitor channel 5
5 ACT ACT I Active high device enable
6 GND GND - Power ground
7 SLEEP SLEEP I Active low sleep enable
8 VDD VDD - Power supply rail
9 SYNC/MON8 - I/O Sequence logging synchronization across multiple devices/Voltage monitor channel 8
9 - NRST O Open Drain Reset Output
10 MON2 MON2 I Voltage monitor channel 2
11 RS_1/2/MON7 RS_1/2 I Voltage monitor channel 1/2 remote sense/Voltage monitor channel 7
12 MON1 MON1 I Voltage monitor channel 1
13 NIRQ NIRQ O Active-low open-drain interrupt output
14 ADDR ADDR I I2C address select pin
15 SDA SDA I/O I2C data pin
16 SCL SCL I I2C clock pin
17 GND GND - Exposed power ground pad