SNVSBM4D March   2022  – October 2024 TPS389006-Q1 , TPS389R0-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I2C
      2. 7.3.2  Auto Mask (AMSK)
      3. 7.3.3  Packet Error Checking (PEC)
      4. 7.3.4  VDD
      5. 7.3.5  MON
      6. 7.3.6  NIRQ
      7. 7.3.7  ADC
      8. 7.3.8  Time Stamp
      9. 7.3.9  NRST
      10. 7.3.10 Register Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS389006/08-Q1,TPS389R0-Q1 Power ON
      3. 7.4.3 General Monitoring
        1. 7.4.3.1 IDLE Monitoring
        2. 7.4.3.2 ACTIVE Monitoring
        3. 7.4.3.3 Sequence Monitoring 1
          1. 7.4.3.3.1 ACT Transitions 0→1
          2. 7.4.3.3.2 SLEEP Transition 1→0
          3. 7.4.3.3.3 SLEEP Transition 0→1
        4. 7.4.3.4 Sequence Monitoring 2
          1. 7.4.3.4.1 ACT Transition 1→0
    5. 7.5 Register Maps
      1. 7.5.1 BANK0 Registers
      2. 7.5.2 BANK1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Multichannel Sequencer and Monitor
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.1 Device Nomenclature

Table 9-1Table 9-2 and Table 9-3 show how to decode the function of the device based on the part number.

Table 9-1 Device Thresholds TPS389006-Q1,TPS389R06-Q1
ORDERING CODE Thresholds VMON1 (V) VMON2 (V) VMON3 (V) VMON4 (V) VMON5 (V) VMON6 (V)

TPS389006ADJRTER

 UV_HF/OV_HF

0.47/0.53

0.47/0.53

0.66/0.74

0.66/0.74

0.66/0.74

0.66/0.74
UV_LF/OV_LF

0.5/0.7

0.5/0.7

0.5/0.7

0.5/0.7

0.5/0.7

0.5/0.7

TPS389006007RTER

 UV_HF/OV_HF

1.4/2.1

1.4/2.1

1.4/2.1

1.4/2.1

1.4/2.1

1.4/2.1
UV_LF/OV_LF

1.4/2.1

1.4/2.1

1.4/2.1

1.4/2.1

1.4/2.1

1.4/2.1

TPS389R06ADJRTER

Preview		 UV_HF/OV_HF

0.705/0.795

0.705/0.795

0.705/0.795

0.705/0.795

3.1/3.5

4.7/5.3
UV_LF/OV_LF

0.705/0.795

0.705/0.795

0.705/0.795

0.705/0.795

3.1/3.5

4.7/5.3
Table 9-2 Device Thresholds TPS389008-Q1
ORDERING CODE Thresholds VMON1 (V) VMON2 (V) VMON3 (V) VMON4 (V) VMON5 (V) VMON6 (V) VMON7 (V) VMON8 (V)

TPS389008M6HRTER

Preview

 UV_HF/OV_HF

0.83/0.91

1.68/1.92

1.68/1.92

0.81/0.91

0.70/0.80

1.005/1.09

0.46/0.535

1.68/1.92
UV_LF/OV_LF

TPS389008M62RTER

Preview

 UV_HF/OV_HF

0.705/0.80

0.805/0.90

1.05/1.18

1.13/1.27

0.70/0.80

1.035/1.165

3.1/3.5

2.24/2.56
UV_LF/OV_LF

TPS389008M67RTER

Preview

 UV_HF/OV_HF

0.775/0.825

1.165/1.235

0.775/0.825

1.165/1.235

0.815/0.865

1.165/1.235

1.74/1.86

4.74/5.26
UV_LF/OV_LF

TPS389008M64RTER

Preview

 UV_HF/OV_HF

0.755/0.845

0.5/1.0

1.05/1.18

0.80/0.90

1.68/1.92

0.755/0.845

1.68/1.92

1.05/1.15
UV_LF/OV_LF

TPS389008M66RTER

Preview

 UV_HF/OV_HF

1.03/1.155

4.7/5.3

1.13/1.27

1.12/1.25

0.755/0.845

3.1/3.5

1.03/1.155

4.74/5.26
UV_LF/OV_LF
Table 9-3 Device Configuration Table
ORDERING CODE FUNCTIONS SCALING OV/UV DEBOUNCE LF CUTOFF I2C ADDRESS BIST SEQ TIMEOUT/RESET DELAY PEC(1) I2C PULL-UP VOLTAGE (V)

ACT/SLEEP

TPS389006ADJRTER

 Monitor LF/HF

1/1/1/1/1/1

 102.4μsec 1kHz Resistor strap at POR 25ms/NA Disable 3.3

Level

TPS389006007RTER

 Monitor LF/HF

4/4/4/4/4/4

25.6μsec

1kH

Resistor Strap

At POR

100ms/NA

Disable

3.3

Level

TPS389R06ADJRTER Preview

 Monitor LF/HF

1/1/1/1/4/4

51.2μsec

1kH

Resistor Strap

At POR

50ms/20ms

Disable

3.3

Level

TPS389008M6xRTER Preview

 Monitor LF/HF 1 or 4 based on thresholds

51.2μsec

1kH

Resistor Strap

At POR

100ms/NA

Disable

3.3

Level
(1) For parts with PEC enabled:
  1. PEC calculation is based on initializing to 0x00.
  2. In case of a PEC violation there needs to be a subsequent I2C transaction before NIRQ is asserted.
  3. If incorrect PEC device asserts NIRQ.
  4. If there is an extra byte after successfully writing the correct PEC byte, NIRQ is asserted and the write fails.