SNVSBM4D March   2022  – October 2024 TPS389006-Q1 , TPS389R0-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I2C
      2. 7.3.2  Auto Mask (AMSK)
      3. 7.3.3  Packet Error Checking (PEC)
      4. 7.3.4  VDD
      5. 7.3.5  MON
      6. 7.3.6  NIRQ
      7. 7.3.7  ADC
      8. 7.3.8  Time Stamp
      9. 7.3.9  NRST
      10. 7.3.10 Register Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS389006/08-Q1,TPS389R0-Q1 Power ON
      3. 7.4.3 General Monitoring
        1. 7.4.3.1 IDLE Monitoring
        2. 7.4.3.2 ACTIVE Monitoring
        3. 7.4.3.3 Sequence Monitoring 1
          1. 7.4.3.3.1 ACT Transitions 0→1
          2. 7.4.3.3.2 SLEEP Transition 1→0
          3. 7.4.3.3.3 SLEEP Transition 0→1
        4. 7.4.3.4 Sequence Monitoring 2
          1. 7.4.3.4.1 ACT Transition 1→0
    5. 7.5 Register Maps
      1. 7.5.1 BANK0 Registers
      2. 7.5.2 BANK1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Multichannel Sequencer and Monitor
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
7.4.3.3.1 ACT Transitions 0→1
TPS389006-Q1 TPS389R0-Q1 ACT 0→1 Transition Figure 7-14 ACT 0→1 Transition

  1. The TPS389006/08-Q1,TPS389R0-Q1 takes several actions on the ACT 0→1 transition:
    1. The synchronization counter is reset to 0.
    2. The REC_ACTIVE bit is set, and SEQ[1:0] bits are updated to 00b.
    3. If the sequence overwrite bit is enabled (EN_SEQ_OW=1), the sequence logging registers (SEQ_ON_LOG[N]) are overwritten with new data. If there was data in the registers that was not read by the host (SEQ_ON_RDY still set), the sequence overwrite flag (SEQ_ON_OW) gets set.
    4. If the timestamps overwrite bit is enabled (EN_TS_OW=1), the timestamp logging registers (SEQ_TIME_xSB[N]) are overwritten with new data. If there was data in the registers that was not read by the host (TS_RDY still set), the timestamp overwrite flag (TS_OW) is set.
    5. If the sequence overwrite bit is disabled (EN_SEQ_OW=0) and there was data in the registers SEQ_ON_LOG[N] that was not read and acknowledged by the host (SEQ_ON_RDY still set), the sequence overwrite flag (SEQ_ON_OW) is set and does not overwrite the registers with new data.
    6. If the timestamp overwrite bit is disabled (EN_TS_OW=0) and there was data in the registers SEQ_TIME_xSB[N] that was not read and acknowledged by the host (TS_RDY still set), the timestamp overwrite flag (TS_OW) is set and does not overwrite the registers with new data.
    7. The internal sequence timer is (re)started.
  2. All TPS389006/08-Q1,TPS389R0-Q1 inputs selected with auto-mask register AMSK_ON start with masked (disabled) interrupts for Undervoltage Low Frequency (UVLF), Undervoltage High Frequency (UVHF), and Overvoltage High Frequency (OVHF) conditions.
  3. As each rail passes the UVLF threshold (UV_LF[N]), automatically (and expected to happen within about 5-10μs) the relevant UV and OV interrupts are unmasked and enabled/disabled according to the IEN_UVLF, IEN_UVHF, and IEN_OVHF registers.
  4. As each rail passes the UVLF or OFF threshold (depending on SEQ_UP_THLD.OFF_UV[N] register setting), the rail is tagged with a counter corresponding to the order of rising edge transition. A timestamp is also logged.
    1. the tag value stored in the relevant status register SEQ_ON_LOG[N] if allowed as per overwrite settings and status. also, the timestamp of the event is stored in registers SEQ_TIME_MSB[N] and SEQ_TIME_LSB[N] as allowed by the overwrite settings and status.
    2. the SEQ_ON_LOG[N] register is compared to the expected sequence order value defined in register SEQ_EXP[N], and an interrupt is generated if different and if the relevant interrupt enable bit is set (IEN_SEQ_ON). Note that if overwrite settings and recording status do not allow writing new data to the logging registers, then the comparison cannot be performed and no interrupt will be generated.
  5. After a timeout, tagging stops.
    1. Clear the REC_ACTIVE bit.
    2. If rails are up with the correct sequence, TPS389006/08-Q1,TPS389R0-Q1 is in ACTIVE state and starts normal monitoring.
    3. If any rail has a tag not matching the configured value in SEQ_ON_EXP[N] register, NIRQ is asserted. The TPS389006/08-Q1,TPS389R0-Q1 continues normal monitoring.
    4. If SLEEP is low, the TPS389006/08-Q1,TPS389R0-Q1 will not start recording the Sleep Entry sequence, as sequence recording is started on ACT and SLEEP transitions, or when initiated through I2C command.