Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS4005x uses voltage feedforward control, the gain of the PWM modulator with voltage feedforward circuit must be included. The generic modulator gain is described in Figure 7-5. Duty cycle, D, varies from 0 to 1 as the control voltage, V_C, varies from the minimum ramp voltage to the maximum ramp voltage, V_S. Also, for a synchronous buck converter, D = V_O / V_IN. To get the control voltage to output voltage modulator gain in terms of the input voltage and ramp voltage:

Equation 11.

With the voltage feedforward function, the ramp slope is proportional to the input voltage. Therefore, the moderator DC gain is independent to the change of input voltage.

For the TPS4005x, with V_IN(min) being the minimum input voltage required to cause the ramp excursion to reach the maximum ramp amplitude of V_RAMP, the modulator DC gain is shown in Equation 12.

Equation 12.

For a buck converter using voltage mode control, there is a double pole due to the output L-C_O. The double pole is located at the frequency calculated in Equation 13.

Equation 13.

There is also a zero created by the output capacitance, C_O, and its associated ESR. The ESR zero is located at the frequency calculated in Equation 14.

Equation 14.

Calculate the value of R_BIAS to set the output voltage, V_O.

Equation 15.

The maximum crossover frequency (0 dB loop gain) is set by Equation 16.

Equation 16.

Typically, f_C is selected to be close to the midpoint between the L-C_O double pole and the ESR zero. At this frequency, the control to output gain has a –2 slope (–40 dB/decade), while the Type III topology has a +1 slope (20 dB/decade), resulting in an overall closed loop –1 slope (–20 dB/decade). Figure 7-6 shows the modulator gain, L-C filter, output capacitor ESR zero, and the resulting response to be compensated.

Figure 7-5 PWM Modulator Relationships

Figure 7-6 Modulator Gain vs Switching Frequency

A Type III topology, shown in Figure 7-7, has two zero-pole pairs in addition to a pole at the origin. The gain and phase boost of a Type III topology is shown in Figure 7-8. The two zeros are used to compensate the L-C_O double pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide controlled gain roll-off. In many cases, the second pole can be eliminated and the gain roll-off of the amplifier is used to roll-off the overall gain at higher frequencies.

Figure 7-7 Type III Compensation Configuration

Figure 7-8 Type III Compensation Gain and Phase

The poles and zeros for a Type III network are described in Equation 17 through Equation 20.

Equation 17.

Equation 18.

Equation 19.

Equation 20.

The value of R1 is somewhat arbitrary, but influences other component values. A value between 50 kΩ and 100 kΩ usually yields reasonable values.

The unity gain frequency is described in Equation 21.

Equation 21.

where

• G is the reciprocal of the modulator gain at f_C.

The modulator gain as a function of frequency at f_C is described in Equation 22.

Equation 22.

Care must be taken not to load down the output of the error amplifier with the feedback resistor, R2, that is too small. The error amplifier has a finite output source and sink current, which must be considered when sizing R2. A value that is too small does not allow the output to swing over its full range.

Equation 23.