SLUSBT2A January   2014  – August 2014 TPS51604-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
    7. 6.7 Typical Power Block MOSFET Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 UVLO Protection
      2. 7.3.2 PWM Pin
      3. 7.3.3 SKIP Pin
        1. 7.3.3.1 Zero Crossing (ZX) Operation
      4. 7.3.4 Adaptive Dead-Time Control and Shoot-Through Protection
      5. 7.3.5 Integrated Boost-Switch
  8. 8 Layout
    1. 8.1 Layout Guidelines
  9. 9 Device and Documentation Support
    1. 9.1 Trademarks
    2. 9.2 Electrostatic Discharge Caution
    3. 9.3 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DSG
8 PINS
(TOP VIEW)
po_pinout_SLUSBT2.gif

Pin Functions

PIN I/O(1) DESCRIPTION
NAME NO.
BST 1 I High-side N-channel FET bootstrap voltage input; power supply for high-side driver
DRVH 8 O High-side N-channel gate drive output
DRVL 5 O Synchronous low-side N-channel gate drive output
GND 6 — Synchronous low-side N-channel gate drive return and IC reference
PWM 2 I PWM input. A tri-state voltage on this pin turns OFF both the high-side (DRVH) and low-side drivers (DRVL)
SKIP 3 I When SKIP is LO, the zero crossing comparator is active; the power chain enters discontinuous conduction mode when the inductor current reaches zero. When SKIP is HI, the zero crossing comparator is disabled, and the driver outputs follow the PWM input. A tri-state voltage on SKIP puts the driver into a very-low power state.
SW 7 I/O High-side N-channel gate drive return. Also, zero-crossing sense input
Thermal Pad — Tie to system GND plane with multiple vias
VDD 4 I 5-V power supply input; decouple to GND with a ceramic capacitor with a value of 1 µF or greater
(1) I = Input, O = Output