TPS53667 6-Phase, D-CAP+, Step-Down, Buck Controller with NVM and PMBus™ Interface for ASIC Power and High-Current Point-of-Load

1 Features

• 8-bit Selectable BOOT Voltage via Pinstrap or NVM: 0.5 V to 2.5 V (down to 5-mV Step)
• 1-, 2-, 3-, 4-, 5-, or 6- Phase Operation
• PMBus™ System Interface for Telemetry of Voltage, Current, Power, Temperature, and Fault Conditions
• 1.8-V and 3.3-V PMBus Bias Compatible
• Fault Reporting: Output Voltage, Output Current, and Temperature
• Configurable with Non-Volatile Memory (NVM) or Resistor Pinstrap
• 16 Levels of Programmable Per-Phase OCL with Pinstrap or NVM
• Fast Transient with DCAP+™Control
• Optimized Efficiency at Light and Heavy Loads
• Support Pre-Bias Startup
• Phase Current Imbalance Detection and Reporting
• 8 Independent Levels of Overshoot Reduction (OSR) and Undershoot Reduction (USR)
• Driverless Configuration for Efficient High-Frequency Switching
• Compatible with CSD9549x NexFET™ Power Stages
• Accurate, Adjustable Voltage Positioning
• 300-kHz to 1-MHz Frequency Selections with Closed-loop Frequency Control
• Patented AutoBalance™ Phase Balancing
• Uses TI’s Fusion Digital Power Designer GUI
• Dynamic Phase Shedding with Programmable Current Threshold
• Conversion Voltage Range: 4.5 V to 17 V
• Small, 6 mm × 6 mm, 40-Pin, QFN, PowerPAD™ Package

2 Applications

• Application-Specific Integrated Circuit (ASIC) Power in Communications Equipment
• High Density Power Solutions
• Server Power
• Smart Power Systems

3 Description

The TPS53667 is a high-current, multi-phase, step-down controller. The device offers built-in non volatile memory (NVM) and PMBus interface. It is compatible with the NexFET power stages (CSD9549x). The TPS53667 provides 8-bit BOOT voltage selection covering output voltage from 0.5 V to 2.5 V, with steps as small as 5 mV, which is ideal for high current application with accurate output voltage setting. Advanced control features such as D-CAP+ architecture with undershoot reduction (USR) and overshoot reduction (OSR) provide fast transient response, lowest output capacitance, and high efficiency. The TPS53667 also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at light loads. In addition, the TPS53667 supports the PMBus communication interface with systems for telemetry of voltage, current, power, temperature, and fault conditions. Some of the configurations can be programmed by pinstrap or PMBus and stored in non-volatile memory to minimize the external component count.

The TPS53667 is offered in a space saving, thermally enhanced 40-pin QFN package and is rated to operate from –40°C to 125°C.

1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

4 Revision History

Changes from A Revision (September 2016) to B Revision

• Updated V3R3 LDO sectionGo
• Added temperature default value VR_HOT and VR_FAULT Indication sectionGo
• Corrected factory default value of VOUT_OV_FAULT_RESPONSE command in Table 7Go
• Corrected factory default value of VIN_OV_FAULT_LIMIT command in Table 7Go
• Corrected factory default value of MFR_ID command in Table 7Go
• Corrected factory default value of MFR_SPECIFIC_44 command in Table 7Go

Changes from * Revision (July 2016) to A Revision

• Changed data sheet status from Product Preview to Production DataGo
• Added Receiving Notification of Documentation Updates sectionGo
• Added Community Resources sectionGo

5 Pin Configuration and Functions

RTA Package

40-Pin QFN

Top View

Pin Functions

PIN		I/O(1)	DESCRIPTION
NAME	NO.
ADDR-TRISE	28	I	Voltage divider to VREF pin. A resistor (RADDR-TRISE) connected between this pin and GND sets the 3-bits. Bit 2 and bit 1 set the rise slew rate. Bit 0 Selects the LSB of BOOT voltage. The voltage (VADDR-TRISE) sets 4 bits PMBus address. The device latches these settings when V3R3 powers up.
COMP	11	O	Output of the gM error amplifier. Resistors and capacitors connected between this pin and the VREF pin set the compensation.
CSP1	3	I	Positive current sense inputs. Connect to the IOUT pin of TI smart power stages (ex: CSD9549x). Tie CSP6, CSP5, CSP4, CSP3, or CSP2 to the V3R3 pin according to Table 3 to disable the corresponding phase.
CSP2	4
CSP3	5
CSP4	6
CSP5	7
CSP6	8
ENABLE	23	I	VR enable. 1-V I/O level; 100-ns debounce.
F-IMAX	32	I	Voltage divider to VREF pin. A resistor (RF-IMAX) connected between this pin and GND sets the operating frequency of the controller. The voltage level (VF-IMAX) sets the maximum operating current of the converter. The IMAX value is an 8-bit A/D where VF-IMAX = VVREF × IMAX / 255. Both are latched at V3R3 power-up.
GND	17	G	Ground pin.
GND	20	G	Connect these pins to GND. Note this is not IC ground pin.
	22
IMON	2	O	Analog current monitor output.
ISUM	12	O	A resistor (RISUM) connected between this pin and VREF pin determines the droop. (where n is the number of phases)
OCL-R	1	I	A resistor (ROCL-R) connected between this pin and GND and the voltage level (VOCL-R) select 1 of 16 OCL levels (per phase current-limit). VOCL-R also sets one of four RAMP levels. The device latches these settings when V3R3 powers up.
O-USR	30	I	Voltage divider to VREF pin. A resistor (RO-USR) connected between this pin and GND selects one of seven OSR thresholds or OFF. The voltage level (VO-USR) sets one of seven USR levels or OFF. The device latches these settings when V3R3 powers up.
PMB_ALERT	25	O	I2C PMBus interrupt line. Open drain. 3.3-V and 1.8-V logic level.
PMB_CLK	24	I	I2C PMBus clock. 3.3-V and 1.8-V logic level.
PMB_DIO	26	I/O	I2C PMBus digital I/O line. 3.3-V and 1.8-V logic level.
PWM1	38	O	PWM signals for each phase
PWM2	37
PWM3	36
PWM4	35
PWM5	34
PWM6	33
RESET	21	I	Reset pin. If this pin is low for more than 1000 ns, the controller pulls the output voltage to the VBOOT level.
SKIP-NVM	39	O	A resistor (R SKIP-NVM) connected between this pin and GND sets either pinstrap or NVM configuration mode. This pin can also connect to the FCCM pin of TI smart power stages (ex: CSD9549x) for SKIP or FCCM operation.
SLEW-MODE	29	I	Voltage divider to VREF pin. A resistor (RSLEW-MODE) connected between this pin and GND sets 8 slew rates. The voltage level (VSLEW-MODE) sets 4-bit operation modes. Bit 7 for DAC mode (1 for VR12.0; 0 for VR12.5). Bit 6 for the 4-phase interleaving mode (1 for 1/3 and 2/4 two phase interleaving; 0 for 4 phase interleaving individually). Bit 4 for enabling dynamic phase add or drop (1 for enable; 0 for disable). Bit 3 sets zero load-line (1 for zero load-line; 0 for non-zero load-line) The device latches these settings when V3R3 powers up.
TSEN	40	I	Connect to the TAO/FAULT pin of TI smart power stages (ex: CSD9549x) to sense the highest temperature of the power stages and to sense the fault signal from the power stages.
V3R3	14	O	3.3-V LDO output. Bypass this pin to GND with a ceramic capacitor with a value of 1-µF or larger.
V5	15	P	5-V power input. Bypass this pin to GND with a ceramic capacitor with a value of 1-µF or larger. This pin is used to power all internal analog circuits.
VBOOT	31	I	Voltage divider to VREF pin. A resistor (RVBOOT) connected between this pin and GND sets 3 bits (B[3:1]). The voltage level (VVBOOT) sets 4 bits (B[7:4]). The total 7 bits set 7 of 8 bits of VID of boot voltage (B[7:1]). The device latches these settings when V3R3 powers up.
VIN	16	P	Input voltage supply. This pin is also used for input voltage sensing for on-time control and input undervoltage lockout (UVLO).
VR_RDY	18	O	Power good open-drain output for the controller. This pin is typically pulled up to V3R3 pin through a resistor with a value of 3-kΩ or larger.
VR_FAULT	27	O	VR fault indicator (open-drain). The failures include shorts of the high-side FETs, over temperature, output overvoltage, and overcurrent conditions of the input. The fault signal should be used on the platform to remove the power source either by firing a shunting SCR to blow a fuse or by turning off the AC power supply. When the failure occurs, the VR_FAULT pin is LOW. This pin is typically pulled up to V3R3 pin through a resistor with a value of 3-kΩ or larger. Leave this pin floating if not used.
VR_HOT	19	O	Thermal flag open drain output. Active low. This pin is typically pulled up to V3R3 pin through a resistor with a value of 3-kΩ or larger. Leave this pin floating if not used.
VREF	13	O	1.7-V, 500-µA, LDO reference voltage. Bypass this pin to GND with a ceramic capacitor with a value of 0.33 µF. Connect the VREF pin to the REFIN pin of TI smart power stages (ex: CSD9549x) as the current-sense reference voltage.
VSN	10	I	Negative input of the remote voltage sense amplifier. Connect this pin directly to the GND of the load.
VSP	9	I	Positive input of the remote voltage sense amplifier. Connect this pin directly to the load.
Thermal Pad		GND	Thermal pad. Connect the thermal pad to the ground plane with multiple vias.

(1) I = Input, O = Output, P = Power, I/O = Bi-directional, GND = ground