JAJSH64B November   2012  – April 2019 TPS53819A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Soft-Start
      2. 7.3.2  Adaptive On-Time Control
      3. 7.3.3  Zero Crossing Detection
      4. 7.3.4  Output Discharge Control
      5. 7.3.5  Low-Side Driver
      6. 7.3.6  High-Side Driver
      7. 7.3.7  Power Good
      8. 7.3.8  Current Sense and Overcurrent Protection
      9. 7.3.9  Overvoltage and Undervoltage Protection
      10. 7.3.10 Out-of-Bound Protection
      11. 7.3.11 UVLO Protection
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light-Load Condition in Auto-Skip Operation (Eco-mode)
      2. 7.4.2 Forced Continuous Conduction Mode
      3. 7.4.3 D-CAP2™ Mode
    5. 7.5 Programming
      1. 7.5.1 PMBus General Descriptions
      2. 7.5.2 PMBus Slave Address Selection
      3. 7.5.3 PMBus Address Selection
      4. 7.5.4 Supported Formats
        1. 7.5.4.1 Direct Format: Write
        2. 7.5.4.2 Combined Format: Read
        3. 7.5.4.3 Stop-Separated Reads
      5. 7.5.5 Supported PMBus Commands
      6. 7.5.6 Unsupported PMBus Commands
    6. 7.6 Register Maps
      1. 7.6.1  OPERATION [01h] (R/W Byte)
      2. 7.6.2  ON_OFF_CONFIG [02h] (R/W Byte)
      3. 7.6.3  WRITE_PROTECT [10h] (R/W Byte)
      4. 7.6.4  CLEAR_FAULTS [03h] (Send Byte)
      5. 7.6.5  STORE_DEFAULT_ALL [11h] (Send Byte)
      6. 7.6.6  RESTORE_DEFAULT_ALL [12h] (Send Byte)
      7. 7.6.7  STATUS_WORD [79h] (Read Word)
      8. 7.6.8  CUSTOM_REG (MFR_SPECIFIC_00) [D0h] (R/W Byte)
      9. 7.6.9  DELAY_CONTROL (MFR_SPECIFIC_01) [D1h] (R/W Byte)
      10. 7.6.10 MODE_SOFT_START_CONFIG (MFR_SPECIFIC_02) [D2h] (R/W Byte)
      11. 7.6.11 FREQUENCY_CONFIG (MFR_SPECIFIC_03) [D3h] (R/W Byte)
      12. 7.6.12 VOUT_ADJUSTMENT (MFR_SPECIFIC_04) [D4h] (R/W Byte)
      13. 7.6.13 Output Voltage Fine Adjustment Soft Slew Rate
      14. 7.6.14 VOUT_MARGIN (MFR_SPECIFIC_05) [D5h] (R/W Byte)
      15. 7.6.15 Output Voltage Margin Adjustment Soft-Slew Rate
      16. 7.6.16 UVLO_THRESHOLD (MFR_SPECIFIC_06) [D6h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Inductor (L1)
        4. 8.2.2.4  Output Capacitors (C10, C11, C12, C13, C14)
        5. 8.2.2.5  Input Capacitors (C1, C2, C3, C4, C5)
        6. 8.2.2.6  MOSFET (Q1, Q2)
        7. 8.2.2.7  VREG Bypass Capacitor (C18)
        8. 8.2.2.8  VDD Bypass Capacitor (C19)
        9. 8.2.2.9  VBST Capacitor (C7)
        10. 8.2.2.10 Snubber (C8 and R9)
        11. 8.2.2.11 Feedback Resistance, RFBH and RFBL (R17 and R18)
        12. 8.2.2.12 Overcurrent Limit (OCL) Setting Resistance (R10)
        13. 8.2.2.13 PMBus Device Address (R3 and R4)
        14. 8.2.2.14 PGOOD Pullup Resistor (R2)
        15. 8.2.2.15 SCL and SDA Pulldown Resistors (R14 and R15)
        16. 8.2.2.16 PMBus Pullup Resistors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

over operating free-air temperature range, VVREG = 5 V, VEN = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IVDD VDD bias current TA = 25°C, no load, power conversion enabled (no switching) 920 μA
IVDDSTBY VDD standby current TA = 25°C, no load, power conversion disabled 610 μA
INTERNAL REFERENCE AND FEEDBACK REGULATION VOLTAGE
VFB Feedback regulation voltage FB w/r/t GND, CCM condition 600 mV
VFBTOL Feedback voltage tolerance FB w/r/t GND, 0°C ≤ TJ ≤ 85°C 597 600 603 mV
VDACTOL1 DAC voltage tolerance 1 FB w/r/t GND, 0°C ≤ TA ≤ 85°C, all settings with VOUT_ADJUSTMENT only –4.8 4.8 mV
VDACTOL2 DAC voltage tolerance 2 FB w/r/t GND, 0°C ≤ TA ≤ 85°C, all settings with VOUT_MARGIN only –4.8 4.8 mV
VDACTOL3 DAC voltage tolerance 3 FB w/r/t GND, 0°C ≤ TA ≤ 85°C, with VOUT_ADJUSTMENT = 0Dh and VOUT_MARGIN = 70h for +5% –4.8 4.8 mV
VDACTOL4 DAC voltage tolerance 4 FB w/r/t GND, 0°C ≤ TA ≤ 85°C, with VOUT_ADJUSTMENT = 13h and VOUT_MARGIN = 07h for -5% –4.8 4.8 mV
VIOS_LPCMP Loop comparator input offset voltage VREF to VFB, TA = 25°C –2.5 2.5 mV
IFB FB pin input current VFB = 600 mV –1 1 μA
OUTPUT VOLTAGE
IVODIS VO discharge current VVO = 0.5 V, power conversion disabled 10 12 mA
DRIVER
RDRVH DRVH resistance Source, IDRVH = 50 mA 1.6 Ω
Sink, IDRVH = 50 mA 0.6
RDRVL DRVL resistance Source, IDRVL = 50 mA 0.9
Sink, IDRVL = 50 mA 0.5
INTERNAL BOOT STRAP SWITCH
VF Forward voltage VVREG-VBST, TA = 25°C, IF = 10 mA 0.1 0.2 V
IVBST VBST leakage current TA = 25°C, VVBST = 33 V, VSW = 28 V 0.01 1.5 μA
ENABLE LOGIC THRESHOLD
VL EN low-level voltage 0.5 V
VH EN high-level voltage 1.8 V
VHYST EN hysteresis voltage 0.22 V
ILEAK EN input leakage current -1 0 1 μA
POWER GOOD COMPARATOR
VPGTH Powergood threshold PGOOD in from higher 105% 108% 111%
PGOOD in from lower 89% 92% 95%
PGOOD out to higher 113% 116% 119%
PGOOD out to lower 81% 84% 87%
IPG PGOOD sink current VPGOOD = 0.5 V 6.9 mA
IPGLK PGOOD leakage current VPGOOD = 5.0 V -1 0 1 μA
CURRENT DETECTION
ITRIP TRIP source current TA = 25°C, VTRIP = 0.4 V, RDS(on) sensing 9 10 11 μA
TCITRIP TRIP source current temperature coefficient(1) RDS(on) sensing 4700 ppm/°C
VTRIP TRIP voltage range RDS(on) sensing 0.2 3 V
VOCLP Positive current limit threshold VTRIP = 3.0 V, RDS(on) sensing 360 375 390 mV
VTRIP = 1.6 V, RDS(on) sensing 190 200 210
VTRIP = 0.2 V, RDS(on) sensing 20 25 30
VOCLN Negative current limit threshold VTRIP = 3.0 V, RDS(on) sensing –390 –375 –360 mV
VTRIP = 1.6 V, RDS(on) sensing –212 –200 –188
VTRIP = 0.2 V, RDS(on) sensing –30 –25 –20
VZC Zero cross detection offset 0 mV
PROTECTIONS
VVREGUVLO VREG UVLO threshold voltage Wake-up 3.32 V
Shutdown 3.11
VOVP OVP threshold voltage OVP detect voltage 117% 120% 123%
tOVPDLY OVP propagation delay time With 100-mV overdrive 430 ns
VUVP UVP threshold voltage UVP detect voltage 65% 68% 71%
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold Shutdown temperature 140 °C
Hysteresis 40
LDO VOLTAGE
VREG LDO output voltage VIN = 12 V, ILOAD = 10 mA 4.5 5 5.5 V
VDOVREG LDO low droop drop-out voltage VIN = 4.5 V, ILOAD = 30 mA, TA = 25°C 365 mV
ILDO(max) LDO overcurrent limit(1) VIN = 12 V, TA = 25°C 152 mA
VDD UVLO VOLTAGE
VDDUVLO VDD UVLO voltage VDDINUVLO<2:0> = 0xx 10.2 V
VDDINUVLO<2:0> = 101 4.1 4.25 4.4
VDDINUVLO<2:0> = 110 6.0
VDDINUVLO<2:0> = 111 8.1
VDDHY-UVLO VDD UVLO hysteresis voltage 0°C ≤ TJ ≤ 85°C 0.2 V
PMBus SCL and SDA INPUT BUFFER LOGIC THRESHOLDS
VIL-PMBUS SCL and SDA low-level input voltage(1) 0°C ≤ TJ ≤ 85°C 0.8 V
VIH-PMBUS SCL and SDA high-level input voltage(1) 0°C ≤ TJ ≤ 85°C 2.1 V
VHY-PMBUS SCL and SDA hysteresis voltage(1) 0°C ≤ TJ ≤ 85°C 240 mV
PMBus SDA and ALERT OUTPUT PULLDOWN
VOL1-PMBUS SDA and ALERT low-level output voltage(1) VDDPMBus = 5.5 V,
RPULLUP = 1.1 kΩ, 0°C ≤ TJ ≤ 85°C		 0.4 V
VOL2-PMBUS SDA and ALERT low-level output voltage(1) VDDPMBus = 3.6 V,
RPULLUP = 0.7 kΩ, 0°C ≤ TJ ≤ 85°C		 0.4 V
(1) Specified by design. Not production tested.