JAJSH64B November   2012  – April 2019 TPS53819A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Soft-Start
      2. 7.3.2  Adaptive On-Time Control
      3. 7.3.3  Zero Crossing Detection
      4. 7.3.4  Output Discharge Control
      5. 7.3.5  Low-Side Driver
      6. 7.3.6  High-Side Driver
      7. 7.3.7  Power Good
      8. 7.3.8  Current Sense and Overcurrent Protection
      9. 7.3.9  Overvoltage and Undervoltage Protection
      10. 7.3.10 Out-of-Bound Protection
      11. 7.3.11 UVLO Protection
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light-Load Condition in Auto-Skip Operation (Eco-mode)
      2. 7.4.2 Forced Continuous Conduction Mode
      3. 7.4.3 D-CAP2™ Mode
    5. 7.5 Programming
      1. 7.5.1 PMBus General Descriptions
      2. 7.5.2 PMBus Slave Address Selection
      3. 7.5.3 PMBus Address Selection
      4. 7.5.4 Supported Formats
        1. 7.5.4.1 Direct Format: Write
        2. 7.5.4.2 Combined Format: Read
        3. 7.5.4.3 Stop-Separated Reads
      5. 7.5.5 Supported PMBus Commands
      6. 7.5.6 Unsupported PMBus Commands
    6. 7.6 Register Maps
      1. 7.6.1  OPERATION [01h] (R/W Byte)
      2. 7.6.2  ON_OFF_CONFIG [02h] (R/W Byte)
      3. 7.6.3  WRITE_PROTECT [10h] (R/W Byte)
      4. 7.6.4  CLEAR_FAULTS [03h] (Send Byte)
      5. 7.6.5  STORE_DEFAULT_ALL [11h] (Send Byte)
      6. 7.6.6  RESTORE_DEFAULT_ALL [12h] (Send Byte)
      7. 7.6.7  STATUS_WORD [79h] (Read Word)
      8. 7.6.8  CUSTOM_REG (MFR_SPECIFIC_00) [D0h] (R/W Byte)
      9. 7.6.9  DELAY_CONTROL (MFR_SPECIFIC_01) [D1h] (R/W Byte)
      10. 7.6.10 MODE_SOFT_START_CONFIG (MFR_SPECIFIC_02) [D2h] (R/W Byte)
      11. 7.6.11 FREQUENCY_CONFIG (MFR_SPECIFIC_03) [D3h] (R/W Byte)
      12. 7.6.12 VOUT_ADJUSTMENT (MFR_SPECIFIC_04) [D4h] (R/W Byte)
      13. 7.6.13 Output Voltage Fine Adjustment Soft Slew Rate
      14. 7.6.14 VOUT_MARGIN (MFR_SPECIFIC_05) [D5h] (R/W Byte)
      15. 7.6.15 Output Voltage Margin Adjustment Soft-Slew Rate
      16. 7.6.16 UVLO_THRESHOLD (MFR_SPECIFIC_06) [D6h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Inductor (L1)
        4. 8.2.2.4  Output Capacitors (C10, C11, C12, C13, C14)
        5. 8.2.2.5  Input Capacitors (C1, C2, C3, C4, C5)
        6. 8.2.2.6  MOSFET (Q1, Q2)
        7. 8.2.2.7  VREG Bypass Capacitor (C18)
        8. 8.2.2.8  VDD Bypass Capacitor (C19)
        9. 8.2.2.9  VBST Capacitor (C7)
        10. 8.2.2.10 Snubber (C8 and R9)
        11. 8.2.2.11 Feedback Resistance, RFBH and RFBL (R17 and R18)
        12. 8.2.2.12 Overcurrent Limit (OCL) Setting Resistance (R10)
        13. 8.2.2.13 PMBus Device Address (R3 and R4)
        14. 8.2.2.14 PGOOD Pullup Resistor (R2)
        15. 8.2.2.15 SCL and SDA Pulldown Resistors (R14 and R15)
        16. 8.2.2.16 PMBus Pullup Resistors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6.7 STATUS_WORD [79h] (Read Word)

The TPS53819A does not support all functions of the STATUS_WORD command. A list of supported functions appears in Table 7. A status bit reflects the current state of the converter. Status bit becomes high when the specified condition has occurred and goes low when the specified condition has disappeared. A flag bit is a latched bit that becomes high when the specified condition has occurred and does not go back low when the specified condition has disappeared. STATUS_BYTE command is a subset of the STATUS_WORD command, or more specifically the lower byte of the STATUS_WORD.

Table 7. STATUS_WORD Command Supported Functions

COMMAND DEFINITION DESCRIPTION
LOW BYTE: STATUS_BYTE [78h]
Low STATUS_WORD<7> BUSY not supported and always set to 0
Low STATUS_WORD<6> OFF 0: raw status indicating device is providing power to output voltage
1: raw status indicating device is not providing power to output voltage
Low STATUS_WORD<5> VOUT_OV 0: latched flag indicating no output voltage overvoltage fault has occurred
1: latched flag indicating an output voltage overvoltage fault has occurred
Low STATUS_WORD<4> IOUT_OC 0: latched flag indicating no output current overcurrent fault has occurred
1: latched flag indicating an output current overcurrent fault has occurred
Low STATUS_WORD<3> VIN_UV 0: latched flag indicating input voltage is above the UVLO turn-on threshold
1: latched flag indicating input voltage is below the UVLO turn-on threshold
Low STATUS_WORD<2> TEMP 0: latched flag indicating no OT fault has occurred
1: latched flag indicating an OT fault has occurred
Low STATUS_WORD<1> CML 0: latched flag indicating no communication, memory or logic fault has occurred
1: latched flag indicating a communication, memory or logic fault has occurred
Low STATUS_WORD<0> OTHER not supported and always set to 0
HIGH BYTE
High STATUS_WORD<7> VOUT 0: latched flag indicating no output voltage fault or warning has occurred
1: latched flag indicating a output voltage fault or warning has occurred
High STATUS_WORD<6> IOUT 0: latched flag indicating no output current fault or warning has occurred
1: latched flag indicating an output current fault or warning has occurred
High STATUS_WORD<5> INPUT 0: latched flag indicating no input voltage fault or warning has occurred
1: latched flag indicating a input voltage fault or warning has occurred
High STATUS_WORD<4> MFR not supported and always set to 0
High STATUS_WORD<3> PGOOD 0: raw status indicating PGOOD pin is at logic high
1: raw status indicating PGOOD pin is at logic low
High STATUS_WORD<2> FANS not supported and always set to 0
High STATUS_WORD<1> OTHER not supported and always set to 0
High STATUS_WORD<0> UNKNOWN not supported and always set to 0

The latched flags of faults can be removed or corrected only until one of the following conditions occurs:

  • The device receives a CLEAR_FAULTS command.
  • The output is commanded through the EN pin and/or ON_OFF bit based on the ON_OFF_CONFIG setting to turn off and then to turn back on
  • VDD power is cycled for TPS53819A

If the fault condition remains present when the bit is cleared, the fault bits are immediately set again, and the ALERT signal is re-asserted.

TPS53819A supports the ALERT pin to notify the host of fault conditions. Therefore, the best practice for monitoring the fault conditions from the host is to treat the ALERT pin as an interrupt source for triggering the corresponding interrupt service routine. It is recommended not to keep polling the STATUS_WORD or STATUS_BYTE registers from the host to reduce the firmware overhead of the host.