10.1 Layout Guidelines

Note these design considerations before starting a layout work using TPS53819A

• Inductor, V_IN capacitors, V_OUT capacitors and MOSFETs are the power components and should be placed on one side of the PCB (solder side). Other small signal components can be placed on another side (component side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the small signal traces from noisy power lines.
• Place all sensitive analog traces and components such as FB, VO, TRIP, PGOOD, and EN away from high-voltage switching nodes such as SW, DRVL, DRVH or VBST to avoid coupling. Use internal layers as ground planes and shield feedback trace from power traces and components.
• Keep PMBus interfacing signals away from the sensitive analog traces.
• The DC/DC converter has several high-current loops. Minimize the area of these loops in order to suppress switching noise.
  • The path from the V_IN capacitors through the high and low-side MOSFETs and back to the capacitors through ground, is the most important loop area to minimize. Connect the negative node of the V_IN capacitors and the source of the low-side MOSFET at ground as close as possible.
  • The second important loop is the path from the low-side MOSFET through inductor and V_OUT capacitors, and back to source of the low-side MOSFET through ground. Connect source of the low-side MOSFET and negative node of V_OUT capacitors at ground as close as possible.
  • The third important loop is that of the gate driving system for the low-side MOSFET. To turn on the low-side MOSFET, high current flows from the VDRV capacitor through the gate driver and the low-side MOSFET, and back to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current flows from gate of the low-side MOSFET through the gate driver and PGND of the device, and back to source of the low-side MOSFET through ground. Connect the negative node of the VREG capacitor, source of the low-side MOSFET and PGND of the device at ground as close as possible.
• A separate AGND from the high-current loop PGND should be used for the return of the sensitive analog circuitry. The two grounds should connect at a single point as close to the GND pin as possible.
• Minimize the current loop from the VDD and VREG pins through their respective capacitors to the GND pin.
• Because the TPS53819A controls the output voltage referring to voltage across V_OUT capacitor, the top-side resistor of the voltage divider should be connected to the positive node of the V_OUT capacitor. In a same manner both bottom side resistor and GND of the device should be connected to the negative node of V_OUT capacitor. The trace from these resistors to the VFB pin should be short and thin. Place on the component side and avoid vias between these resistors and the device.
• Connect the overcurrent setting resistor from the TRIP pin to ground and make the connections as close as possible to the device. Avoid coupling a high-voltage switching node to the trace from the TRIP pin to R_TRIP and from R_TRIP to ground .
• Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and vias of at least 0.5 mm (20 mils) diameter along this trace.
• The PCB trace defined as switch node, which connects to source of high-side MOSFET, drain of low-side MOSFET and high-voltage side of the inductor, should be as short and wide as possible.
• Follow any layout considerations for the MOSFET provided by the MOSFET manufacturer.