The TPS5401 device is a 42-V, 0.5-A, step-down regulator with an integrated high-side MOSFET. Current-mode control provides simple external compensation and flexible component selection. A low-ripple pulse-skip mode reduces the supply current to 116 μA when outputting regulated voltage with no load. Using the enable pin, shutdown supply current is reduced to 1.3 μA when the enable pin is low.
Undervoltage lockout is internally set at 2.5 V, but can be increased using the enable pin. The output voltage start-up ramp is controlled by the slow-start pin that can also be configured for sequencing/tracking. An open-drain power-good signal indicates the output is within 94% to 107% of its nominal voltage.
A wide switching-frequency range allows efficiency and external component size optimization. Frequency foldback and thermal shutdown protect the part during an overload condition.
The TPS5401 is available in a 10-pin thermally enhanced MSOP PowerPAD package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS5401 | MSOP (10) | 3.00 mm × 3.00 mm |
Changes from A Revision (December 2010) to B Revision
Changes from * Revision (December 2010) to A Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO. | |||
BOOT | 1 | O | A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed. | |
COMP | 8 | O | Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin. | |
EN | 3 | I | Enable pin, internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. | |
GND | 9 | – | Ground | |
PH | 10 | O | The source of the internal high-side power MOSFET | |
PWRGD | 6 | O | An open-drain output; asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage or EN shutdown. | |
RT/CLK | 5 | I | Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high-impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to a resistor-set function. | |
SS/TR | 4 | I | Slow-start and tracking. An external capacitor connected to this pin sets the output rise time. Because the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing. | |
VIN | 2 | I | Input supply voltage, 3.5 V to 42 V. | |
VSENSE | 7 | I | Inverting node of the transconductance (gm) error amplifier. | |
Thermal pad | (11) | – | GND pin must be electrically connected to the thermal pad on the printed circuit board for proper operation. |