SLVSCO3B August   2016  – October 2016 TPS54116-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Bootstrap Voltage (BOOT) and Low Dropout Operation
      3. 7.3.3  Error Amplifier
      4. 7.3.4  Voltage Reference and Adjusting the Output Voltage
      5. 7.3.5  Enable and Adjusting Undervoltage Lockout
      6. 7.3.6  Soft Start and Tracking
      7. 7.3.7  Start-up into Pre-Biased Output
      8. 7.3.8  Power Good
      9. 7.3.9  Sequencing
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/SYNC)
      11. 7.3.11 Buck Overcurrent Protection
      12. 7.3.12 Overvoltage Transient Protection
      13. 7.3.13 VTT Sink and Source Regulator
      14. 7.3.14 VTTREF
      15. 7.3.15 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Inductor Selection
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Input Capacitor
        5. 8.2.2.5  Soft Start Capacitor
        6. 8.2.2.6  Undervoltage Lock Out Set Point
        7. 8.2.2.7  Bootstrap Capacitor
        8. 8.2.2.8  Power Good Pullup
        9. 8.2.2.9  ILIM Resistor
        10. 8.2.2.10 Output Voltage and Feedback Resistors Selection
        11. 8.2.2.11 Compensation
        12. 8.2.2.12 LDOIN Capacitor
        13. 8.2.2.13 VTTREF Capacitor
        14. 8.2.2.14 VTT Capacitor
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C6
  • Single-chip DDR2, DDR3 and DDR3L Memory Power Solution
  • 4-A Synchronous Buck Converter
    • Integrated 33-mΩ High-side and 25-mΩ Low-side MOSFETs
    • Fixed Frequency Current-mode Control
    • Adjustable Frequency from 100 kHz to 2.5 MHz
    • Synchronizable to an External Clock
    • 0.6-V ±1% Voltage Reference Over Temperature
    • Adjustable Cycle-by-Cycle Peak Current Limit
    • Monotonic Start-up Into Pre-biased Outputs
  • 1-A Source/Sink Termination LDO with ±20-mV DC Accuracy
    • Stable with 2 × 10-µF MLCC Capacitor
    • 10-mA Source/Sink Buffered Reference Output Regulated to Within 49% to 51% of VDDQ
  • Independent Enable Pins with Adjustable UVLO and Hysteresis
  • Thermal Shutdown
  • -40°C to 150°C Operating TJ
  • 24-pin, 4-mm x 4-mm WQFN Package

2 Applications

  • DDR2, DDR3, DDR3L, and DDR4 Memory Power Supplies in Embedded Computing Systems
  • SSTL_18, SSTL_15, SSTL_135, SSTL_12 and HSTL Termination
  • Infotainment and Cluster
  • Advanced Driver Assistance Systems (ADAS)

3 Description

The TPS54116-Q1 device is a full featured 6-V, 4-A, synchronous step down converter with two integrated MOSFETs and 1-A sink/source double data rate (DDR) VTT termination regulator with VTTREF buffered reference output.

The TPS54116-Q1 buck regulator minimizes solution size by integrating the MOSFETs and reducing inductor size with up to 2.5-MHz switching frequency. The switching frequency can be set above the medium wave radio band for noise sensitive applications and is synchronizable to an external clock. Synchronous rectification keeps the frequency fixed across the entire output load range. Efficiency is maximized through integrated 25-mΩ low-side and 33-mΩ high-side MOSFETs. Cycle-by-cycle peak current limit protects the device during an overcurrent condition and is adjustable with a resistor at the ILIM pin to optimize for smaller inductors.

The VTT termination regulator maintains fast transient response with only 2 × 10-µF ceramic output capacitance reducing external component count. The TPS54116-Q1 uses remote sensing of VTT for best regulation.

Using the enable pins to enter a shutdown mode reduces supply current to 1-µA. Under voltage lockout thresholds can be set with a resistor network on either enable pin. The VTT and VTTREF outputs are discharged when disabled with ENLDO.

Full integration minimizes the IC footprint with a small 4 mm × 4 mm thermally enhanced WQFN package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS54116-Q1 WQFN (24) 4.00 mm × 4.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

TPS54116-Q1 sco3_simplifiedschematic.gif

4 Revision History

Changes from A Revision (August 2016) to B Revision

  • Changed text From: "double date rate (DDR)" To: "double data rate (DDR)" in the DescriptionGo

Changes from * Revision (August 2016) to A Revision