TPS54260-Q1 3.5-V to 60-V Step-Down Converter With Eco-mode™
1 Features
- Qualified for Automotive Applications
- AEC-Q100 Qualified With the Following Results:
- 3.5-V to 60-V Input Voltage Range
- 200-mΩ High-Side MOSFET
- High Efficiency at Light Loads With a Pulse Skipping Eco-mode™
- 138-μA Operating Quiescent Current
- 1.3-μA Shutdown Current
- 100-kHz to 2.5-MHz Switching Frequency
- Synchronizes to External Clock
- Adjustable Slow Start and Sequencing
- UV and OV Power Good Output
- Adjustable UVLO Voltage and Hysteresis
- 0.8-V Internal Voltage Reference
- 10-Pin HVSSOP and 10-Pin 3-mm × 3-mm VSON Packages
- Supported by WEBENCH® Software Tool
2 Applications
- 12-V and 24-V Automotive and Industrial Systems
- Infotainment, Cluster, and ADAS Applications
3 Description
The TPS54260-Q1 device is a 60-V, 2.5-A, step-down regulator with an integrated high-side MOSFET. Current mode control provides simple external compensation and flexible component selection. A low ripple pulse skip mode reduces the no load, regulated output supply current to 138 μA. Using the enable pin, shutdown supply current is reduced to
1.3-μA, when the enable pin is low.
Under voltage lockout is internally set at 2.5 V, but can be increased using the enable pin. The output voltage startup ramp is controlled by the slow start pin that can also be configured for sequencing and tracking. An open drain power good signal indicates the output is within 94% to 107% of the nominal voltage.
A wide switching frequency range allows efficiency and external component size to be optimized. Frequency fold back and thermal shutdown protects the part during an overload condition.
The TPS54260-Q1 is available in 10-pin thermally-enhanced HVSSOP and 10-pin 3-mm × 3-mm VSON package.
Device Information(1)
| PART NUMBER | PACKAGE | PACKAGE SIZE |
|---|---|---|
| TPS54260-Q1 | HVSSOP (10) | 3.00 mm × 4.90 mm |
| VSON (10) | 3.00 mm × 3.00 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
Space
Simplified Schematic
Efficiency vs Load Current
4 Revision History
Changes from E Revision (December 2014) to F Revision
- Added package information for VSON to the Device Information tableGo
- Added pinout drawing for DRC package (VSON) Go
- Removed max ratings for BOOT voltage Go
- Added minimum output voltage for BOOT-PH Go
- Added thermal information for DRC (VSON) package Go
- Updated Rth parameter definition for Equation 55Go
- Added Community ResourcesGo
Changes from D Revision (January 2013) to E Revision
- Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
Changes from C Revision (May 2013) to D Revision
- Changed PWRGD from 10 kΩ to 1 kΩ in Power Good (PWRGD Pin) sectionGo
Changes from B Revision (January, 2013) to C Revision
- Changed Feature From: Device CDM ESD Classification Level C4B To: Device CDM ESD Classification Level C5Go
- Changed the CDM From: Classification Level C4B, 750 V To: Classification Level C5, 1000 VGo
Changes from A Revision (April, 2011) to B Revision
5 Pin Configuration and Functions
Pin Functions
| PIN | I/O | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | NO. | |||
| BOOT | 1 | O | A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed. | |
| COMP | 8 | O | Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin. | |
| EN | 3 | I | Enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. | |
| GND | 9 | — | Ground | |
| PH | 10 | I | The source of the internal high-side power MOSFET. | |
| PowerPAD | — | — | GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation. | |
| PWRGD | 6 | O | An open-drain output, asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage or EN shut down. | |
| RT/CLK | 5 | I | Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to a resistor set function. | |
| SS/TR | 4 | I | Slow-start and Tracking. An external capacitor connected to this pin sets the output rise time. Because the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing. | |
| VIN | 2 | I | Input supply voltage, 3.5 to 60 V | |
| VSENSE | 7 | I | Inverting node of the transconductance (gm) error amplifier | |
