JAJS448D March   2010  – October 2018 TPS54260

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と負荷電流との関係
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency PWM Control
      2. 8.3.2  Slope Compensation Output Current
      3. 8.3.3  Pulse-Skip Eco-Mode
      4. 8.3.4  Low-Dropout Operation and Bootstrap Voltage (BOOT)
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Voltage Reference
      7. 8.3.7  Adjusting the Output Voltage
      8. 8.3.8  Enable and Adjusting Undervoltage Lockout
      9. 8.3.9  Slow-Start / Tracking Pin (SS/TR)
      10. 8.3.10 Overload Recovery Circuit
      11. 8.3.11 Sequencing
      12. 8.3.12 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      13. 8.3.13 Overcurrent Protection and Frequency Shift
      14. 8.3.14 Selecting the Switching Frequency
      15. 8.3.15 How to Interface to RT/CLK Pin
      16. 8.3.16 Powergood (PWRGD Pin)
      17. 8.3.17 Overvoltage Transient Protection
      18. 8.3.18 Thermal Shutdown
      19. 8.3.19 Small Signal Model for Loop Response
      20. 8.3.20 Simple Small Signal Model for Peak Current Mode Control
      21. 8.3.21 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation Near Minimum Input Voltage
      2. 8.4.2 Operation With Enable Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 3.3-V Output Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2  Selecting the Switching Frequency
          3. 9.2.1.2.3  Output Inductor Selection (LO)
          4. 9.2.1.2.4  Output Capacitor
          5. 9.2.1.2.5  Catch Diode
          6. 9.2.1.2.6  Input Capacitor
          7. 9.2.1.2.7  Slow-Start Capacitor
          8. 9.2.1.2.8  Bootstrap Capacitor Selection
          9. 9.2.1.2.9  Undervoltage Lock Out Set Point
          10. 9.2.1.2.10 Output Voltage and Feedback Resistors Selection
          11. 9.2.1.2.11 Compensation
          12. 9.2.1.2.12 Discontinuous Mode and Eco-Mode Boundary
          13. 9.2.1.2.13 Power Dissipation Estimate
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Inverting Power Supply
      3. 9.2.3 Split-Rail Power Supply
      4. 9.2.4 12-V to 3.8-V GSM Power Supply
      5. 9.2.5 24-V to 4.2-V GSM Power Supply
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
        1. 12.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 3.5 to 60 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 3.5 60 V
Internal undervoltage lockout threshold No voltage hysteresis, rising and falling 2.5 V
Shutdown supply current EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V 1.3 4 μA
Operating: nonswitching supply current VSENSE = 0.83 V, VIN = 12 V, 25°C 138 200
ENABLE AND UVLO (EN PIN)
Enable threshold voltage No voltage hysteresis, rising and falling 1.15 1.25 1.36 V
Input current Enable threshold +50 mV –3.8 μA
Enable threshold –50 mV –0.9
Hysteresis current –2.9 μA
VOLTAGE REFERENCE
Voltage reference TJ = 25°C 0.792 0.8 0.808 V
0.784 0.8 0.816
HIGH-SIDE MOSFET
On-resistance VIN = 3.5 V, BOOT-PH = 3 V 300 mΩ
VIN = 12 V, BOOT-PH = 6 V 200 410
ERROR AMPLIFIER
Input current 50 nA
Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V 310 μS
Error amplifier transconductance (gM) during slow-start –2 μA < ICOMP < 2 μA, VCOMP = 1 V,
VVSENSE = 0.4 V		 70 μS
Error amplifier dc gain VVSENSE = 0.8 V 10,000 V/V
Error amplifier bandwidth 2700 kHz
Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive ±27 μA
COMP to switch current transconductance 10.5 S
CURRENT LIMIT
Current limit threshold VIN = 12 V, TJ = 25°C 3.5 6.1 A
THERMAL SHUTDOWN
Thermal shutdown 182 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode 100 2500 kHz
fSW Switching frequency RT = 200 kΩ 450 581 720 kHz
Switching frequency range using CLK mode 300 2200 kHz
Minimum CLK input pulse width 40 ns
RT/CLK high threshold 1.9 2.2 V
RT/CLK low threshold 0.5 0.7 V
RT/CLK falling edge to PH rising edge delay Measured at 500 kHz with RT resistor in series 60 ns
PLL lock in time Measured at 500 kHz 100 μs
SLOW-START AND TRACKING (SS/TR)
Charge current VSS/TR = 0.4 V 2 μA
SS/TR-to-VSENSE matching VSS/TR = 0.4 V 45 mV
SS/TR-to-reference crossover 98% nominal 1.15 V
SS/TR discharge current (overload) VSENSE = 0 V, V(SS/TR) = 0.4 V 382 μA
SS/TR discharge voltage VSENSE = 0 V 54 mV
POWERGOOD (PWRGD PIN)
VVSENSE VSENSE threshold VSENSE falling 92%
VSENSE rising 94%
VSENSE rising 109%
VSENSE falling 107%
Hysteresis VSENSE falling 2%
Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C 10 nA
On resistance I(PWRGD) = 3 mA, VSENSE < 0.79 V 50 Ω
Minimum VIN for defined output V(PWRGD) < 0.5 V, II(PWRGD) = 100 μA 0.95 1.5 V