JAJSCB6B May   2016  – April 2021 TPS54302

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency PWM Control
      2. 7.3.2  Pulse Skip Mode
      3. 7.3.3  Error Amplifier
      4. 7.3.4  Slope Compensation and Output Current
      5. 7.3.5  Enable and Adjusting Undervoltage Lockout
      6. 7.3.6  Safe Startup into Pre-Biased Outputs
      7. 7.3.7  Voltage Reference
      8. 7.3.8  Adjusting Output Voltage
      9. 7.3.9  Internal Soft-Start
      10. 7.3.10 Bootstrap Voltage (BOOT)
      11. 7.3.11 Overcurrent Protection
        1. 7.3.11.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.11.2 Low-Side MOSFET Overcurrent Protection
      12. 7.3.12 Spread Spectrum
      13. 7.3.13 Output Overvoltage Protection (OVP)
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Eco-mode™ Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 TPS54302 8-V to 28-V Input, 5-V Output Converter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Input Capacitor Selection
        2. 8.2.3.2 Bootstrap Capacitor Selection
        3. 8.2.3.3 Output Voltage Set Point
        4. 8.2.3.4 Undervoltage Lockout Set Point
        5. 8.2.3.5 Output Filter Components
          1. 8.2.3.5.1 Inductor Selection
          2. 8.2.3.5.2 Output Capacitor Selection
          3. 8.2.3.5.3 Feedforward Capacitor
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
  • DDC|6
サーマルパッド・メカニカル・データ
発注情報

10.1 Layout Guidelines

Follow these layout guidelines:

  • The VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of advantage from the view point of heat dissipation.
  • The input capacitor and output capacitor should be placed as close to the device as possible to minimize trace impedance.
  • Provide sufficient vias for the input capacitor and output capacitor.
  • Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
  • Do not allow switching current to flow under the device.
  • A separate VOUT path should be connected to the upper feedback resistor.
  • Make a Kelvin connection to the GND pin for the feedback path.
  • The voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has ground shield.
  • The trace of the VFB node should be as small as possible to avoid noise coupling.
  • The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its trace impedance.