JAJSCB6B
May 2016 – April 2021
TPS54302
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Fixed-Frequency PWM Control
7.3.2
Pulse Skip Mode
7.3.3
Error Amplifier
7.3.4
Slope Compensation and Output Current
7.3.5
Enable and Adjusting Undervoltage Lockout
7.3.6
Safe Startup into Pre-Biased Outputs
7.3.7
Voltage Reference
7.3.8
Adjusting Output Voltage
7.3.9
Internal Soft-Start
7.3.10
Bootstrap Voltage (BOOT)
7.3.11
Overcurrent Protection
7.3.11.1
High-Side MOSFET Overcurrent Protection
7.3.11.2
Low-Side MOSFET Overcurrent Protection
7.3.12
Spread Spectrum
7.3.13
Output Overvoltage Protection (OVP)
7.3.14
Thermal Shutdown
7.4
Device Functional Modes
7.4.1
Normal Operation
7.4.2
Eco-mode™ Operation
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
TPS54302 8-V to 28-V Input, 5-V Output Converter
8.2.2
Design Requirements
8.2.3
Detailed Design Procedure
8.2.3.1
Input Capacitor Selection
8.2.3.2
Bootstrap Capacitor Selection
8.2.3.3
Output Voltage Set Point
8.2.3.4
Undervoltage Lockout Set Point
8.2.3.5
Output Filter Components
8.2.3.5.1
Inductor Selection
8.2.3.5.2
Output Capacitor Selection
8.2.3.5.3
Feedforward Capacitor
8.2.4
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.2
Receiving Notification of Documentation Updates
11.3
サポート・リソース
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
DDC|6
サーマルパッド・メカニカル・データ
発注情報
jajscb6b_oa
jajscb6b_pm
10.2
Layout Example
Figure 10-1
Board Layout